1. Figure 5.1. Conversion from decimal to binary.

2. Table 5.1. Numbers in different systems.

3. Figure 5.2. Half-adder. Please see “portrait orientation” PowerPoint file for Chapter 5

4. Figure 5.3. An example of addition.

5. Figure 5.4. Full-adder. Please see “portrait orientation” PowerPoint file for Chapter 5

6. Figure 5.5. A decomposed implementation of the full-adder circuit. HA s c s c c i x i y i c i1+ s i c i x i y i c i1+ s i (a) Block diagram (b) Detailed diagram

7. Figure 5.6. An n-bit ripple-carry adder. FA x n –1 c n c n1” y n1– s n1– FA x 1 c 2 y 1 s 1 c 1 x 0 y 0 s 0 c 0 MSB positionLSB position

8. Figure 5.7. Circuit that multiplies an 8-bit unsigned number by 3. Please see “portrait orientation” PowerPoint file for Chapter 5

9. Figure 5.8. Formats for representation of integers. b n1– b 1 b 0 Magnitude MSB (a) Unsigned number b n1– b 1 b 0 Magnitude Sign (b) Signed number b n2– 0 denotes 1 denotes + –MSB

10. Table 5.2. Interpretation of four-bit signed integers.

11. Figure 5.9. Examples of 1’s complement addition. ++ 1 1 0 0 1 0 0 0 1 0 0 1 1 1 0 1 0 0 1 0 ++ 0 1 1 1 1 0 1 1 0 1 0 0 1 0 0 1 1 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 2+ () 5–  3-  + 5–  7–  + 2–  5+ () 2+ () 7+ () + 5+ () 3+ () + 2– 

12. Figure 5.10. Examples of 2’s complement addition. ++ 1 1 0 1 1 0 1 1 0 0 1 0 0 1 1 1 0 1 0 0 1 0 ++ 1 0 0 1 1 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 0 11 ignore 5+ () 2+ () 7+ () + 5+ () 3+ () + 2–  2+ () 5–  3–  + 5–  7–  + 2– 

13. Figure 5.11. Examples of 2’s complement subtraction. – 0 1 0 0 1 0 5+ () 2+ () 3+ () – 1 ignore + 0 0 1 1 0 1 1 1 1 0 – 1 0 1 1 0 0 1 0 – 1 ignore + 1 0 0 1 1 0 1 1 1 1 1 0 – 0 1 1 1 1 0 5+ () 7+ () – + 0 1 1 1 0 1 0 0 1 0 5–  7–  2+ () 2–  – 1 0 1 1 1 1 1 0 – + 1 1 0 1 1 0 1 1 0 0 1 02–  5–  3– 

14. Figure 5.12. Graphical interpretation of four-bit 2’s complement numbers. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1+1– 2+ 3+ 4+ 5+ 6+ 7+ 2– 3– 4– 5– 6– 7– 8– 0

15. Figure 5.13. Adder/subtractor unit. s 0 s 1 s n1– x 0 x 1 x n1– c n n-bit adder y 0 y 1 y n1– c 0 Add  Sub control

16. Figure 5.14. Examples of determination of overflow. ++ 1 0 1 1 1 0 0 1 0 0 1 0 1 0 0 1 0 1 1 1 0 0 1 0 7+ () 2+ () 9+ () + ++ 0 1 1 1 1 0 0 1 1 1 1 0 0 1 0 1 1 1 1 1 1 0 7+ () 5+ () + 2–  11 c 4 0= c 3 1= c 4 0= c 3 0= c 4 1= c 3 1= c 4 1= c 3 0= 2+ () 7–  5–  + 7–  9–  +2– 

17. x 1 y 1 g 1 p 1 s 1 Stage 1 x 0 y 0 g 0 p 0 s 0 Stage 0 c 0 c 1 c 2 Figure 5.15. A ripple-carry adder with generate/propagate signals.

18. Figure 5.16. The first two stages of a carry-lookahead adder. x 1 y 1 g 1 p 1 s 1 x 0 y 0 s 0 c 2 x 0 y 0 c 0 c 1 g 0 p 0

19. Figure 5.17. A hierarchical carry-lookahead adder with ripple-carry between blocks. Block x 3124– c 32 c 24 y 3124– s 3124– x 158– c 16 y 158– s 8– c 8 x 70– y 70– s 70– c 0 3 Block 1 0

20. Figure 5.18. A hierarchical carry-lookahead adder. Block x 158– y 8– x 70– y 70– 3 Block 1 0 Second-level lookahead c 0 s 70– P 0 G 0 P 1 G 1 P 3 G 3 s 158– s 3124– c 8 c 16 c 32 x 3124– y 3124– c

21. Figure 5.19. An alternative design for a carry-lookahead adder. x 1 y 1 g 1 p 1 s 1 s 0 c 2 x 0 y 0 c 0 c 1 g 0 p 0

22. Figure 5.20. Schematic using an LPM adder/subtractor module.

23. Figure 5.21. Simulation results for the LPM adder optimized for cost.

24. Figure 5.22. Simulation results for the LPM adder optimized for speed.

25. Figure 5.23. Verilog code for the full-adder using gate level primitives. module fulladd (Cin, x, y, s, Cout); input Cin, x, y; output s, Cout; xor (s, x, y, Cin); and (z1, x, y); and (z2, x, Cin); and (z3, y, Cin); or (Cout, z1, z2, z3); endmodule

26. Figure 5.24. Another version of Verilog code from Figure 5.23. module fulladd (Cin, x, y, s, Cout); input Cin, x, y; output s, Cout; xor (s, x, y, Cin); and (z1, x, y), (z2, x, Cin), (z3, y, Cin); or (Cout, z1, z2, z3); endmodule

27. Figure 5.25. Verilog code for the full-adder using continuous assignment. module fulladd (Cin, x, y, s, Cout); input Cin, x, y; output s, Cout; assign s = x ^ y ^ Cin; assign Cout = (x & y) | (x & Cin) | (y & Cin); endmodule

28. Figure 5.26. Another version of Verilog code from Figure 5.25. module fulladd (Cin, x, y, s, Cout); input Cin, x, y; output s, Cout; assign s = x ^ y ^ Cin, Cout = (x & y) | (x & Cin) | (y & Cin); endmodule

29. Figure 5.27. Verilog code for a four-bit adder. module adder4 (carryin, x3, x2, x1, x0, y3, y2, y1, y0, s3, s2, s1, s0, carryout); input carryin, x3, x2, x1, x0, y3, y2, y1, y0; output s3, s2, s1, s0, carryout; fulladd stage0 (carryin, x0, y0, s0, c1); fulladd stage1 (c1, x1, y1, s1, c2); fulladd stage2 (c2, x2, y2, s2, c3); fulladd stage3 (c3, x3, y3, s3, carryout); endmodule module fulladd (Cin, x, y, s, Cout); input Cin, x, y; output s, Cout; assign s = x ^ y ^ Cin, assign Cout = (x & y) | (x & Cin) | (y & Cin); endmodule

30. Figure 5.28. A four-bit adder using vectors. module adder4 (carryin, X, Y, S, carryout); input carryin; input [3:0] X, Y; output [3:0] S; output carryout; wire [3:1] C; fulladd stage0 (carryin, X[0], Y[0], S[0], C[1]); fulladd stage1 (C[1], X[1], Y[1], S[1], C[2]); fulladd stage2 (C[2], X[2], Y[2], S[2], C[3]); fulladd stage3 (C[3], X[3], Y[3], S[3], carryout); endmodule

31. Figure 5.29. A generic specification of a ripple-carry adder. module addern (carryin, X, Y, S, carryout); parameter n=32; input carryin; input [n-1:0] X, Y; output [n-1:0] S; output carryout; reg [n-1:0] S; reg carryout; reg [n:0] C; integer k; always @(X or Y or carryin) begin C[0] = carryin; for (k = 0; k < n; k = k+1) begin S[k] = X[k] ^ Y[k] ^ C[k]; C[k+1] = (X[k] & Y[k]) | (X[k] & C[k]) | (Y[k] & C[k]); end carryout = C[n]; end endmodule

32. Figure 5.30. Specification of an n-bit adder using arithmetic assignment. module addern (carryin, X, Y, S); parameter n = 32; input carryin; input [n-1:0] X, Y; output [n-1:0] S; reg [n-1:0] S; always @(X or Y or carryin) S = X + Y + carryin; endmodule

33. Figure 5.31. An n-bit adder with carry-out and overflow signals. module addern (carryin, X, Y, S, carryout, overflow); parameter n = 32; input carryin; input [n-1:0] X, Y; output [n-1:0] S; output carryout, overflow; reg [n-1:0] S; reg carryout, overflow; always @(X or Y or carryin) begin S = X + Y + carryin; carryout = (X[n-1] & Y[n-1]) | (X[n-1] & ~S[n-1]) | (Y[n-1] & ~S[n-1]); overflow = carryout ^ X[n-1] ^ Y[n-1] ^ S[n-1]; end endmodule

34. Figure 5.32. An alternative specification of an n-bit adder with carry-out and overflow signals. module addern (carryin, X, Y, S, carryout, overflow); parameter n = 32; input carryin; input [n-1:0] X, Y; output [n-1:0] S; output carryout, overflow; reg [n-1:0] S; reg carryout, overflow; reg [n:0] Sum; always @(X or Y or carryin) begin Sum = {1'b0,X} + {1'b0,Y} + carryin; S = Sum[n-1:0]; carryout = Sum[n]; overflow = carryout ^ X[n-1] ^ Y[n-1] ^ S[n-1]; end endmodule

35. Figure 5.33. Simplified complete specification of an n-bit adder. module addern (carryin, X, Y, S, carryout, overflow); parameter n = 32; input carryin; input [n-1:0] X, Y; output [n-1:0] S; output carryout, overflow; reg [n-1:0] S; reg carryout, overflow; always @(X or Y or carryin) begin {carryout, S} = X + Y + carryin; overflow = carryout ^ X[n-1] ^ Y[n-1] ^ S[n-1]; end endmodule

36. Figure 5.34. Behavioral specification of a full-adder. module fulladd (Cin, x, y, s, Cout); input Cin, x, y; output s, Cout; reg s, Cout; always @(x or y or Cin) {Cout, s} = x + y + Cin; endmodule

37. Figure 5.35. Multiplication of unsigned numbers. Please see “portrait orientation” PowerPoint file for Chapter 5

38. Figure 5.36. A 4 x 4 multiplier circuit. Please see “portrait orientation” PowerPoint file for Chapter 5

39. Figure 5.37. Multiplication of signed numbers. Please see “portrait orientation” PowerPoint file for Chapter 5

40. Figure 5.38. IEEE standard floating-point formats. Sign 32 bits 23 bits of mantissa excess-127 exponent 8-bit 52 bits of mantissa11-bit excess-1023 exponent 64 bits Sign SM SM (a) Single precision (c) Double precision E + E 0 denotes – 1 denotes

41. Table 5.3. Binary-coded decimal digits.

42. Figure 5.39. Addition of BCD digits. + 1 1 0 0 0 1 1 1 0 1 + X Y Z + 7 5 12 0 1 1 0 + 1 0 0 1 0 carry + 1 0 0 0 1 1 0 0 0 1 0 0 1 + X Y Z + 8 9 17 0 1 1 0 + 1 0 1 1 1 carry S = 2 S = 7

43. Figure 5.40. Block diagram for a one-digit BCD adder.

44. modulebcdadd (Cin,X,Y,S, Cout); inputCin; input[3:0] X,Y; output[3:0] S; outputCout; reg[3:0] S; regCout; reg[4:0] Z; always@ (X orYorCin) begin Z=X+Y+Cin; if(Z<10) {Cout,S}=Z; else {Cout,S}=Z+6; end endmodule Figure 5.41. Verilog code for a one-digit BCD adder.

45. Figure 5.42. Functional simulation of the Verilog code in Figure 5.41.

46. Figure 5.43. Circuit for a one-digit BCD adder.

47. Figure P5.1. Circuit for problem 5.11.

48. Figure P5.2. The code for problem 5.17. module problem5_17 (IN, OUT); input [3:0] IN; output [3:0] OUT; reg [3:0] OUT; always @(IN) if (IN == 4'b0101) OUT = 4'b0001; else if (IN == 4'b0110) OUT = 4'b0010; else if (IN == 4'b0111) OUT = 4'b0011; else if (IN == 4'b1001) OUT = 4'b0010; else if (IN == 4'b1010) OUT = 4'b0100; else if (IN == 4'b1011) OUT = 4'b0110; else if (IN == 4'b1101) OUT = 4'b0011; else if (IN == 4'b1110) OUT = 4'b0110; else if (IN == 4'b1111) OUT = 4'b1001; else OUT = 4'b0000; endmodule

49. Figure P5.3. Ternary half-adder. 0000 0101 0202 1001 1102 1210 2002 2110 2211