1. Orange Coast College Business Division Computer Science Department CS 116- Computer Architecture Logic Design: Part 3

2. OCC - CS/CIS CS116-Ch00-Orientation 2 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 2 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Logic Design Many mathematical & logical operations are difficult or impossible to perform with analog quantities Digital logic: – Maps real world values into two subsets corresponding to possible logic values  0 and 1.

3. OCC - CS/CIS CS116-Ch00-Orientation 3 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 3 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Logic Design Digital electronics: – Operate only with two voltage levels (HIGH & LOW) – All other voltages are temporary & occur while transitioning between the values. – The values & relationships between the two voltages differ from one logic family to the other. – Digital logic circuits can be analyzed and designed using truth tables.

4. OCC - CS/CIS CS116-Ch00-Orientation 4 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 4 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Some terminology Positive logic circuit: – If 0 is assigned to LOW and 1 to HIGH Negative logic circuit: – If 1 is assigned to LOW and 0 to HIGH Asserted logic value: – Logical true (one). De-asserted logic value: – Logical false (zero)

5. OCC - CS/CIS CS116-Ch00-Orientation 5 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 5 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Logic Design- The Components Gates: – The basic building blocks of logic. Combinational logic systems (circuits): – Systems containing no memory – Output depends on the input only Sequential Logic Systems (circuits): – Output depends on both inputs and past sequence of inputs (i.e. stored value) State of a sequential circuit: – A collection of state variables whose values at any one time contain information about the past to know the circuit's future state or behavior – Values are stored in the memory element.

6. OCC - CS/CIS CS116-Ch00-Orientation 6 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 6 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) The different types of circuits Combinational logic circuit – Fully described by a truth table Lists all the combinations of inputs and outputs Sequential circuits – Described by a state table Specifies its output and next states as function of its current state and inputs.

7. OCC - CS/CIS CS116-Ch00-Orientation 7 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 7 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) State Maps We have seen truth tables. What is a State Map?

8. OCC - CS/CIS CS116-Ch00-Orientation 8 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 8 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Karnaugh Maps A graphical representation of logic functions or truth tables. Allows combining product terms to minimize logic functions. Become impractical if we have more than 5 input variables.

9. OCC - CS/CIS CS116-Ch00-Orientation 9 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 9 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Using a Karnaugh Map Create table – Each axis should be labeled with a variable and the value that variable can take B 010 1 A 1 1 – For each cell in the table, insert a 1 where output is 1 – Just leave the other cells blank A B Out 10101010 01010101 00110011

10. OCC - CS/CIS CS116-Ch00-Orientation 10 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 10 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Using a Karnaugh Map Draw a line around adjacent cells with a 1 B 010 1 A 1 1 Construct a logic function that represents the circled areas – Makes it easy to see where a function can be minimized Output = B

11. OCC - CS/CIS CS116-Ch00-Orientation 11 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 11 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) K-Map with 3 variables Same idea, kind of – The list of input values must follow a specific order – Each value is only one bit different than the next Why is this necessary? – Enabled minimization through adjacency 6754 2310 A 0001 11 10 0101 B and C

12. OCC - CS/CIS CS116-Ch00-Orientation 12 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 12 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) An Even Bigger Karnaugh Map 101198 14151312 6754 2310 A and B C and D 00011110 00 10 11 10

13. OCC - CS/CIS CS116-Ch00-Orientation 13 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 13 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) More Karnaugh Maps 3-Variables Karnaugh Map – Minimizing sum-of-products 11 11 A 0001 11 10 0101 B and C Exercise: What is the minimal value?

14. OCC - CS/CIS CS116-Ch00-Orientation 14 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 14 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Incompletely-Specified Functions Functions that have unspecified output for some input combination Unspecified Minterm’s of a function are usually called “Don’t care conditions” – Don’t care terms can have either 0’s or 1’s – Can be used in truth tables & Karnaugh maps for function simplification

15. OCC - CS/CIS CS116-Ch00-Orientation 15 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 15 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Don't Care Sometimes we don't care what the value of the output would be Usually represented with an "X" or a "d" in the truth table. Output don't cares: – Value of an output for some input combination doesn't matter Input don't cares: – When the output depends only on some of the inputs.

16. OCC - CS/CIS CS116-Ch00-Orientation 16 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 16 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Don't Cares- An Example – D is true if the value of A or C is true. We don't care about the value of B. – E is true if A or B is true. We don't care about the value of C. – F is true if exactly one of the inputs is true. We don't care if more than one input is true. 011X1XxX011X1XxX 0011111100111111 0101111101011111 0101010101010101 0011001100110011 0000111100001111 FEDCBA Outputs

17. OCC - CS/CIS CS116-Ch00-Orientation 17 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 17 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Don't Cares The previous truth table has output don't cares. If we simplify the truth table further, we will get both input and output don't cares. 0111XX0111XX 001111001111 010111010111 01001X01001X 00101X00101X 0001X10001X1 FEDCBA Outputs

18. OCC - CS/CIS CS116-Ch00-Orientation 18 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 18 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Don't Cares- A Real Example BCD Counter – Output a 1 when the value is (10) 10 Details – 4-bits needed – Only 10 states are involved. – States 10-15 are never used (Don’t care)

19. OCC - CS/CIS CS116-Ch00-Orientation 19 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 19 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Don't Cares- A Real Example BCD Number table 00000000111111110000000011111111 A 0000000001XXXXXX0000000001XXXXXX 01010101010101010101010101010101 00110011001100110011001100110011 00001111000011110000111100001111 OutDCB

20. OCC - CS/CIS CS116-Ch00-Orientation 20 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 20 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Logic Gates vs Logic Functions Any logic function can be described using three logic operators (AND, OR, NOT) – Each logic operator can be represented as a logic gate Any logic function can be implemented into a logic circuit diagram – Any logic circuit, can be implemented using three types of gates (And, Or, Inverter)

21. OCC - CS/CIS CS116-Ch00-Orientation 21 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 21 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Function Representation Any logic function can be represented as – A sum of products (for output = 1's) – A product of sums (for output = 0's) Inverter And OR NOT AND OR Logic gateLogic function

22. OCC - CS/CIS CS116-Ch00-Orientation 22 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 22 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Logic Gates NOT gate produces the opposite value of its input – NOT Buffer is used to amplify electrical signals – Buffer 1010 0101 Not (A)A 0101 0101 Buffered(A]A

23. OCC - CS/CIS CS116-Ch00-Orientation 23 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 23 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Logic Gates AND gate produces an asserted output if all its inputs are asserted OR gate produces an asserted output if one or more of its input is asserted 00010001 01010101 00110011 A  B BA 01110111 01010101 00110011 A + BBA

24. OCC - CS/CIS CS116-Ch00-Orientation 24 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 24 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Generalization of Logic Gates Logic gates can have more than 2 inputs Fan-in – # input lines to the gate Fan-out – # o/p lies taken from the gate ABCABC ABCABC A * B * C A + B + C

25. OCC - CS/CIS CS116-Ch00-Orientation 25 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 25 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) More Logic Gates There are other types of gates that can be built out of the three essential gates – NAND (  ) : The opposite of AND – NOR (  ): The opposite of OR 11101110 01010101 00110011 A NAND BBA 10001000 01010101 00110011 A NOR BBA

26. OCC - CS/CIS CS116-Ch00-Orientation 26 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 26 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Other Important Logic Gates Other gates – Exclusive-OR (  : Produces an output if inputs differ – Exclusive-NOR (Coincidence/  ): Produces asserted output if inputs are identical 01100110 01010101 00110011 A XOR BBA 10011001 01010101 00110011 A XNOR BBA

27. OCC - CS/CIS CS116-Ch00-Orientation 27 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 27 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Combining Gates How do we build more complex circuits? – Link simple elements together – Examples: (A’ + B)’ = A B’ A’ B C ( A + D ) ‘ B AA B C B A A D

28. OCC - CS/CIS CS116-Ch00-Orientation 28 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 28 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Logic Gates Universality of NAND & NOR Gates – NAND gates can be used to perform each of the Boolean operations. – We can implement any logic expression using only NAND gates. – De Morgan theorem can be used to convert all gates into NANDs. Exercise: – Build the NAND/NOR equivalent for the 3 main logic gates (AND, OR, & NOT)

29. OCC - CS/CIS CS116-Ch00-Orientation 29 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 29 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) How do we evaluate a circuit? Perform all NOT operations (inversions) of single terms Perform all operations within parentheses Perform AND operations Perform OR operations, unless parentheses indicate otherwise

30. OCC - CS/CIS CS116-Ch00-Orientation 30 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 30 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Equivalent Gate Symbols Can be proven by DeMorgan’s theorems X * Y = [X’ + Y’]’ [X * Y]’ = X’ + Y’ X + Y = [X’ * Y’]’ [X + Y]’ = X’ * Y’

31. OCC - CS/CIS CS116-Ch00-Orientation 31 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 31 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Rules for Connecting Logic Circuits One direction from left-to- right Connected lines should be indicated by a node in the circuit diagram Every input to a gate must have either asserted or deasserted Never connect the output of two or more gates with direct wiring B A ??

32. OCC - CS/CIS CS116-Ch00-Orientation 32 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 32 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Combinational Logic Combinational circuit: – May contain any number of logic gates. – No feedback loops. Feedback loop: – A signal path connecting circuit output back to the input of that same circuit.

33. OCC - CS/CIS CS116-Ch00-Orientation 33 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 33 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Combinational Logic Circuit Analysis – Start with Logic Diagram – Produce a formal description of function Truth Tables Circuit Design – Start with Informal Description – Define the inputs and outputs – Specify behaviour Truth tables Equations – Draw logic diagram

34. OCC - CS/CIS CS116-Ch00-Orientation 34 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 34 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Combinational Logic Two-level logic gates: – If the gates are arranges in two levels, one including ANDs and the other ORs. Examples of logic circuits: – Decoders – Encoders – Adders (Half/ Full) – Multiplexors – PLAs

35. OCC - CS/CIS CS116-Ch00-Orientation 35 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 35 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Decoders Converts binary information from n-bit coded input to maximum of 2 n unique outputs – Combinational Circuit Input: – n-bit input combination Output: – 2 n unique outputs – One will be true based on input Enable line – If 0, then all output 0 Each input word produces a different output word code O u t0 O u t 1 O u t2 O u t3 O u t4 O u t5 O u t6 O u t7 Enable 33x8 Decoder

36. OCC - CS/CIS CS116-Ch00-Orientation 36 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 36 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Decoders 2 x 4 Decoder circuit realization A B A B A B’ A’B A’B’ 10001000 01010101 00110011 Out 1BA 01000100 Out 2 00100010 Out 3 00010001 Out 4

37. OCC - CS/CIS CS116-Ch00-Orientation 37 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 37 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Decoders- Practical Example Application: Put data into a specific register Reg i s t er 0 Reg i st er 1 R e g i s t e r n – 1 Reg i s t er n Registe r numbe r W r it e Regis t er da t a n–1 n to2 n de c ode r 0 1 n C C D D C C D D

38. OCC - CS/CIS CS116-Ch00-Orientation 38 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 38 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Encoders Inverse of decoders Output code has fewer bits than the input code. Input: – 2 n (or less) lines Output: – n lines, binary code corresponding to the input Enable line has same effect Out 0 O ut1 Out2 Enable 8x3 Encoder In0 In1 In2 In3 In4 In5 In6 In7

39. OCC - CS/CIS CS116-Ch00-Orientation 39 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 39 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) How do we build an encoder? 4X2 Binary encoder – O1 = A * B – O2 = A * C – Value of D doesn’t affect the output – Use K-map/Don’t Care to find a solution Application: – Convert decimal to BCD A B O2=A’C’ O1=A’B’ C D 111000 010100 100010 000001 O2O1DCBA OutputInput

40. OCC - CS/CIS CS116-Ch00-Orientation 40 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 40 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Multiplexors (MUX/Selectors) Selects binary information – From one of many input lines – Directs this information to a single output line Selection of a particular input is controlled by selector lines Input: – n-input signals, –  log 2 n  selectors Output: – 1 output only Application: – Used in building the CPU to choose specific signals n-Input lines Enable line  log 2 n  Selection lines 1-Output line MUX

41. OCC - CS/CIS CS116-Ch00-Orientation 41 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 41 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Multiplexors (MUX/Selectors) Circuit realization of 2x1 MUX Another symbol representing MUX C A B S A C Select 0 M U X 1 B

42. OCC - CS/CIS CS116-Ch00-Orientation 42 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 42 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Multiplexors- A Practical Example Application: Selecting a register from register file: 1 R e giste r 0 R e giste r 1 R egist er n – R eg i s t e r n Read data 1 Read data 2 Read register number 1 Rea d r eg i s t e r n um b e r 2 Selector signals nx1 MUX 32-bits wide MUXMUX MUXMUX

43. OCC - CS/CIS CS116-Ch00-Orientation 43 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 43 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Binary Half Adder Performs arithmetic addition on two binary input values Half-Adder:Truth table – Adding 2 Bits – Sum = A  B – Carry = A * B Implementation 1011 0101 0110 0000 CarrySumBA ABAB Carry

44. OCC - CS/CIS CS116-Ch00-Orientation 44 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 44 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Binary Full Adders Full adder: – Adding 3 Bits – Sum = A  B  C in – C out = A * B + B * C in + A * C in Implementation: – Three possibilities Use basic logic gates Use 2 Half adders Use ROM 10101 01001 10011 1 0 0 0 0 A 0101 1111 1011 0110 0000 C out SumC in B Truth table

45. OCC - CS/CIS CS116-Ch00-Orientation 45 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 45 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Binary Adders Full adder Implementation : – Using basic logic gates – Using 2 Half adders – Using ROM A B C in Sum Carry H.A. A B C in Sum Carry H.A Sum Carry ROM A B C in Sum Carry

46. OCC - CS/CIS CS116-Ch00-Orientation 46 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 46 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Binary Ripple Adders Ripple-Carry adder : – For more than one binary bit we can cascade the full-adder modules FA A 1 B 1 C in S1S1 C out FA A 3 B 3 C i3 S 3 C out3 FA A 2 B 2 C i2 S 2 C out2

47. OCC - CS/CIS CS116-Ch00-Orientation 47 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 47 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Binary Subtractors Half-Subtractor: – Difference = A  B – Borrow = A’. B – We can make use of the adder to perform subtraction 0011 0101 1110 0000 BorrowDifferenceBA ABAB Borrow

48. OCC - CS/CIS CS116-Ch00-Orientation 48 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 48 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Binary Subtractors We can make use of the adder to perform subtraction – Truth table – Circuit realization 0011 0101 1110 0000 BorrowDifferenceBA ABAB Sum/Difference Borrow Carry

49. OCC - CS/CIS CS116-Ch00-Orientation 49 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 49 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Homework Special Notes