1. CMPUT 329 - Computer Organization and Architecture II1 CMPUT329 - Fall 2003 Topic9: Three-State Buffers, Encoders/Decoders José Nelson Amaral

2. CMPUT 329 - Computer Organization and Architecture II2 Reading Assignment Sections 5.6, 5.7, 5.8, 5.9, 5.10

3. CMPUT 329 - Computer Organization and Architecture II3 Encoders vs. Decoders DecoderEncoder

4. CMPUT 329 - Computer Organization and Architecture II4 Binary encoders We assume that only one input is active at any given time.

5. CMPUT 329 - Computer Organization and Architecture II5 Need priority in most applications We must report the request with highest priority amongst potentially many requests.

6. CMPUT 329 - Computer Organization and Architecture II6 8-input priority encoder We also want to report when there are no requests.

7. CMPUT 329 - Computer Organization and Architecture II7 Priority-encoder logic equations First we define eight intermediate variables H0-H7: H7 = I7 H6 = I6I7’ H5 = I5I6’I7’ H0 = I0I1’I2’I3’I4’I5’I6’I7’ Using these signals, we can define the equations for A2-A0: A2 = H4 + H5 + H6 + H7 A1 = H2 + H3 + H6 + H7 A0 = H1 + H3 + H5 + H7 Finally: IDLE = I0’I1’I2’I3’I4’I5’I6’I7’

8. CMPUT 329 - Computer Organization and Architecture II8 74x148 8-input priority encoder Active-low I/0 Enable Input Group Select or “Got Something” Output Enable Output (to connect with EI of lower priority encoders)

9. CMPUT 329 - Computer Organization and Architecture II9 74x148 Circuit

10. CMPUT 329 - Computer Organization and Architecture II10 74x148 Truth Table

11. CMPUT 329 - Computer Organization and Architecture II11 Cascading Priority Encoders z32-input priority encoder 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 1 1 1

12. CMPUT 329 - Computer Organization and Architecture II12 Cascading Priority Encoders z32-input priority encoder The three least significant bits of the output are simply an OR of the outputs of the individual encoders.

13. CMPUT 329 - Computer Organization and Architecture II13 Cascading Priority Encoders z32-input priority encoder The two most significant bits encode which of the individual encoder “got something”.

14. CMPUT 329 - Computer Organization and Architecture II14 Three-state buffers Output = LOW, HIGH, or Hi-Z. Can tie multiple outputs together, if at most one at a time is driven. AOUT EN

15. CMPUT 329 - Computer Organization and Architecture II15 Different flavors AOUT EN AOUT EN AOUT EN AOUT EN

16. CMPUT 329 - Computer Organization and Architecture II16 A Three-State Party Line

17. CMPUT 329 - Computer Organization and Architecture II17 Timing considerations To prevent fighting, they should go into the Hi-Z state faster then they come out of the Hi-Z state (tpLZ and tpHZ should be less than tpZL tpZH)

18. CMPUT 329 - Computer Organization and Architecture II18 Timing considerations For safety, the control logic should guarantee a dead time on the party line during which no one drives the line.

19. CMPUT 329 - Computer Organization and Architecture II19 Hysteresis: Schmitt-Trigger Inverter

20. CMPUT 329 - Computer Organization and Architecture II20 Immunity to Noise

21. CMPUT 329 - Computer Organization and Architecture II21 Three- state drivers

22. CMPUT 329 - Computer Organization and Architecture II22 Driver applicati on

23. CMPUT 329 - Computer Organization and Architecture II23 Three-state Transceiver

24. CMPUT 329 - Computer Organization and Architecture II24 Transceiver Application

25. CMPUT 329 - Computer Organization and Architecture II25 Three-State in VHDL and STD_ULOGIC In VHDL, there is no explicit language construct for joining three-state outputs into a bus. If a signal is driven in two or more different processes, the VHDL automatically joins them together. I.e., signals that appear on the lefthand side of a signal statement in two or more processes are joined together (as long as they have the appropriate type). An unresolved type has an associated resolution function that is called every time an assignment is made to a signal of that type. When the signal has multiple drivers, the type resolution function resolves the value of the signal.

26. CMPUT 329 - Computer Organization and Architecture II26 IEEE 1164 Declarations for STD_ULOGIC, STD_LOGIC PACKAGE std_logic_1164 IS -- logic state system (unresolved) type STD_ULOGIC is (‘U’, -- Uninitialized ‘X’, -- Forcing Unknown ‘0’, -- Forcing 0 ‘1’,-- Forcing 1 ‘Z’,-- High Impedance ‘W’,-- WeakUnknown ‘L’,-- Weak0 ‘H’,-- Weak1 ‘-’-- Don’t Care ); -- unconstrained array of std_logic TYPE std_ulogic_vector IS ARRAY (NATURAL RANGE <> ) OF std_ulogic; -- resolution function FUNCTION resolved (s : std_ulogic_vector ) return std_ulogic; -- *** industry standard logic type *** SUBTYPE std_logic IS resolved std_ulogic;

27. CMPUT 329 - Computer Organization and Architecture II27 IEEE 1164 package body STD_ULOGIC, STD_LOGIC PACKAGE BODY std_logic_1164 IS -- local type TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic; -- resolution function CONSTANT resolution_table : stdlogic_table := ( ------------------------------------------------------------------------------ --| U X 0 1 ZWLH - | | --------------------------------------------------------------- ( ‘U’, ‘U’,‘U’, ‘U’,‘U’,‘U’,‘U’,‘U’,‘U’ ), -- | U| ( ‘U’,‘X’,‘X’,‘X’,‘X’,‘X’,‘X’,‘X’,‘X’ ), -- | X| ( ‘U’, ‘X’,‘0’,‘X’,‘0’,‘0’,‘0’,‘0’,‘X’ ), -- | 0| ( ‘U’, ‘X’,‘X’,‘1’,‘1’,‘1’,‘1’,‘1’,‘X’ ), -- | 1| ( ‘U’, ‘X’,‘0’,‘1’,‘Z’,‘W’,‘L’,‘H’,‘X’ ), -- | Z| ( ‘U’, ‘X’,‘0’,‘1’,‘W’,‘W’,‘W’, ‘W’,‘X’ ), -- | W| ( ‘U’, ‘X’,‘0’,‘1’,‘L’,‘W’,‘L’, ‘W’,‘X’ ), -- | L| ( ‘U’, ‘X’,‘0’,‘1’,‘H’,‘W’,‘W’, ‘H’,‘X’ ), -- | H| ( ‘U’, ‘X’,‘X’,‘X’,‘X’,‘X’,‘X’, ‘X’,‘X’ ), -- | -| ); Part 1 of 2:

28. CMPUT 329 - Computer Organization and Architecture II28 IEEE 1164 package body STD_ULOGIC, STD_LOGIC FUNCTION resolved (s:std_ulogic_ vector) RETURN std_ulogic IS VARIABLE result:std_ulogic := ‘Z’; -- weakest state default BEGIN -- the test for a single driver is essential otherwise the -- loop would return ‘X’ for a single driver of ‘-’ and that -- would conflict with the value of a single driver unresolved signal. IF (s’LENGTH = 1) THEN RETURN s(s’LOW); ELSE FOR i IN s’RANGE LOOP result := resolution_table(result, s(I)); END LOOP; END IF; RETURN result; END resolved; Part 2 of 2:

29. CMPUT 329 - Computer Organization and Architecture II29 Strenght Precedence Rules When multiple drivers are driving a signal, two strenghts are considered at a time (the output of two processes). The order in which these strengths are considered does not affect the outcome because there is a strong ordering in the resolution_table: ‘U’ > ‘X’ > ‘0’, ‘1’ > ‘W’ > ‘L’, ‘H’ > ‘-’. Thus once a signal is partially resolved to a given value, it is never further resolved to a “weaker” value. A 0/1 and L/H conflict always resolve to a stronger undefined value (‘X’ or ‘W’).

30. CMPUT 329 - Computer Organization and Architecture II30 Three-State Drivers in VHDL library IEEE; use IEEE.std_logic_1164.all; entity V3statex is port ( G_L: in STD_LOGIC; -- Global output enable SEL: in STD_LOGIC_VECTOR (1 downto 0); -- Input select 0, 1, 2, 3 ==> A, B, C, D A, B, C, D: in STD_LOGIC_VECTOR (1 to 8); -- Input buses X: out STD_ULOGIC_VECTOR (1 to 8) -- Output bus (three-state) ); architecture V3states of V3statex is begin process (G_L, SEL, A) begin if G_L=‘0’ and SEL = “00” then X <= To_StdULogicVector(A); else X ‘Z’); end if; end process; Part 1 of 2:

31. CMPUT 329 - Computer Organization and Architecture II31 Three-State Drivers in VHDL (cont.) process (G_L, SEL, B) begin if G_L=‘0’ and SEL = “01” then X <= To_StdULogicVector(B); else X ‘Z’); end if; end process; process (G_L, SEL, C) begin if G_L=‘0’ and SEL = “10” then X <= To_StdULogicVector(C); else X ‘Z’); end if; end process; process (G_L, SEL, D) begin if G_L=‘0’ and SEL = “11” then X <= To_StdULogicVector(D); else X ‘Z’); end if; end process; end V3states; Part 2 of 2:

32. CMPUT 329 - Computer Organization and Architecture II32 2-input XOR gates zLike an OR gate, but excludes the case where both inputs are 1. zXNOR: complement of XOR

33. CMPUT 329 - Computer Organization and Architecture II33 XOR and XNOR symbols X  Y  X’  Y’  (X’  Y)’  (X  Y’)’ (X  Y)’  (X’  Y’)’  (X’  Y)  (X  Y’)

34. CMPUT 329 - Computer Organization and Architecture II34 Gate-level XOR circuits

35. CMPUT 329 - Computer Organization and Architecture II35 Multi-input XOR ySum modulo 2 yParity computation yUsed to generate and check parity bits in computer systems. xDetects any single-bit error

36. CMPUT 329 - Computer Organization and Architecture II36 Parity tree zFaster with balanced tree structure

37. CMPUT 329 - Computer Organization and Architecture II37 Equality Comparators z1-bit comparator z4-bit comparator EQ_L

38. CMPUT 329 - Computer Organization and Architecture II38 Iterative Combinatorial Circuit

39. CMPUT 329 - Computer Organization and Architecture II39 Iterative Comparator Circuit

40. CMPUT 329 - Computer Organization and Architecture II40 8-bit Magnitude Comparator Asserted if all 8 input pairs are equal. Asserted if P[7-0]>Q[7-0]

41. CMPUT 329 - Computer Organization and Architecture II41 Adders zBasic building block is “full adder” y1-bit-wide adder, produces sum and carry outputs

42. CMPUT 329 - Computer Organization and Architecture II42 Adders zBasic building block is “full adder” y1-bit-wide adder, produces sum and carry outputs Cout is one if two or more of the inputs are one. S is one if an odd number of inputs are one.

43. CMPUT 329 - Computer Organization and Architecture II43 Full-adder circuit

44. CMPUT 329 - Computer Organization and Architecture II44 Ripple adder ySpeed limited by carry chain yFaster adders eliminate or limit carry chain x2-level AND-OR logic ==> 2 n product terms x3 or 4 levels of logic, carry lookahead

45. CMPUT 329 - Computer Organization and Architecture II45 Ripple Adders: Time  Complexity The equations for the sum and carry out for a full adder can be simply written as: cout 0 = x 0 y 0 + x 0 cin 0 + y 0 cin 0 s 0 = x 0  y 0  cin 0 cout 1 = x 1 y 1 + x 1 cout 0 + y 1 cout 0 s 1 = x 1  y 1  cout 0

46. CMPUT 329 - Computer Organization and Architecture II46 Ripple Adders: Time  Complexity The equations for the sum and carry out for a full adder can be simply written as: cout 0 = x 0 y 0 + x 0 cin 0 + y 0 cin 0 s 0 = x 0  y 0  cin 0 cout 1 = x 1 y 1 + x 1 (x 0 y 0 + x 0 cin 0 + y 0 cin 0 ) + y 1 (x 0 y 0 + x 0 cin 0 + y 0 cin 0 ) s 1 = x 1  y 1  cout 0

47. CMPUT 329 - Computer Organization and Architecture II47 Ripple Adders: Time  Complexity The equations for the sum and carry out for a full adder can be simply written as: cout 0 = x 0 y 0 + x 0 cin 0 + y 0 cin 0 s 0 = x 0  y 0  cin 0 cout 1 = x 1 y 1 + x 1 (x 0 y 0 + x 0 cin 0 + y 0 cin 0 ) + y 1 (x 0 y 0 + x 0 cin 0 + y 0 cin 0 ) cout 1 = x 1 y 1 + x 1 x 0 y 0 + x 1 x 0 cin 0 + x 1 y 0 cin 0 + y 1 x 0 y 0 + y 1 x 0 cin 0 + y 1 y 0 cin 0 s 1 = x 1  y 1  cout 0

48. CMPUT 329 - Computer Organization and Architecture II48 Ripple Adders: Time  Complexity The equations for the sum and carry out for a full adder can be simply written as: cout 0 = x 0 y 0 + x 0 cin 0 + y 0 cin 0 s 0 = x 0  y 0  cin 0 cout 1 = x 1 y 1 + x 1 x 0 y 0 + x 1 x 0 cin 0 + x 1 y 0 cin 0 + y 1 x 0 y 0 + y 1 x 0 cin 0 + y 1 y 0 cin 0 s 1 = x 1  y 1  cout 0 cout 2 = x 2 y 2 + x 2 cout 1 + y 2 cout 1 s 2 = x 2  y 2  cout 1 Could we have a tradeoff between time and complexity?

49. CMPUT 329 - Computer Organization and Architecture II49 Propagate and Generate We can define two functions that depend only on the value of x i and y i, and do not depend on cin i g i = x i y i The generate carry function: The propagate carry function:p i = x i + y i Now we can define the carry out in terms of the carry in and of these two functions: c i+1 = g i + p i c i

50. CMPUT 329 - Computer Organization and Architecture II50 Carry Equations c 1 = g 0 + p 0 c 0 c 2 = g 1 + p 1 c 1 = g 1 + p 1 (g 0 + p 0 c 0 ) = g 1 + p 1 g 0 + p 1 p 0 c 0 c 3 = g 2 + p 2 c 2 = g 2 + p 2 (g 1 + p 1 g 0 + p 1 p 0 c 0 ) = g 2 + p 2 g 1 + p 2 p 1 g 0 + p 2 p 1 p 0 c 0 c 4 = g 3 + p 3 c 3 = g 3 + p 3 (g 2 + p 2 g 1 + p 2 p 1 g 0 + p 2 p 1 p 0 c 0 ) = g 3 + p 3 g 2 + p 3 p 2 g 1 + p 3 p 2 p 1 g 0 + p 3 p 2 p 1 p 0 c 0

51. CMPUT 329 - Computer Organization and Architecture II51 74x283 4-bit adder zUses carry lookahead internally

52. CMPUT 329 - Computer Organization and Architecture II52 “generate” “propagate” “half sum” carry-in from previous stage

53. CMPUT 329 - Computer Organization and Architecture II53 Ripple carry between groups

54. CMPUT 329 - Computer Organization and Architecture II54 Lookahead carry between groups

55. CMPUT 329 - Computer Organization and Architecture II55 Subtraction zSubtraction is the same as addition of the two’s complement. zThe two’s complement is the bit-by-bit complement plus 1. zTherefore, X – Y = X + Y’ + 1. yComplement Y inputs to adder, set C in to 1. yFor a borrow, set C in to 0.

56. CMPUT 329 - Computer Organization and Architecture II56 Full subtractor = full adder, almost