1. 1 EE 587 SoC Design & Test Partha Pande School of EECS Washington State University pande@eecs.wsu.edu

2. 2 Power & Low Power Design

3. 3 Recent Trends

4. 4 What about power in the future? 0.1 1 10 100 1,000 10,000 ’71’74’78’85’92’00’04’08 Power (Watts) 4004 8008 8080 8085 8086 286 386 486 Pentium ® processors Power Projections Too High! Hot Plate Nuclear Reactor Rocket Nozzle Sun’s Surface Source: Intel

5. 5 Power in CMOS Gate

6. 6 Capacitive Voltage Transitions Follow board notes Ref HJS Chapter 5 (5.8)

7. 7 Logic Function Transition probabilities depend on the style of the logic gates Follow board notes

8. 8 Logic Style Static and Dynamic Logic styles Power is consumed during the precharge operation for Dynamic Logic For dynamic case activity depends only on the signal probability The transition probability is higher in dynamic circuits

9. 9 Circuit Topology The chain implementation might have glitches The tree implementation is balanced and glitch free

10. 10 Short-Circuit Power Finite rise and fall times of the input waveforms result in a direct current path between Vdd and GND Refer to Board Notes

11. 11 Static Power Sub threshold leakage pn junction leakage DC current in the output low state

12. 12 Sub Threshold Leakage As Vt is reduced the subthreshold current increases With decreasing temperature the subthreshold current decreases

13. 13 P-N junction leakage Reverse-bias of source and drain junctions Bottom of the junctions and the channel-facing sidewalls One final form of static power arises in the pseudo-NMOS gates when the output is low

14. 14 Power dissipation in Clocks and I/O Significant power dissipation can occur in clocks in high performance designs Clock switches on every cycle so P= (i.e., α=1) Must compute all gate and wire capacitance associated with the clock and then add them all up Include input capacitance of flops or gated-clock inputs Total clock capacitance can be ~nF range For I/O drivers, there is a typical power dissipation provided for inputs and outputs Need to assume something about switching probability of inputs such as clock, reset, address, data, control

15. 15 Memory and Logic Power Equations Total chip power due to memory and logic is P consists of both dynamic and static terms For dynamic switching, we must determine the activity factors associated with the logic blocks using simulation or probabilistic methods

16. 16 Intel Pentium-II Power Distribution

17. 17 Methods of Reducing Power Architectural Decisions – has the highest impact (parallelism, pipelining, low activity designs, lower frequency operation ) Software – low power instructions, algorithms CAD tools to implement low-power techniques Circuit Techniques – gated clocks, low glitch circuits, reduce capacitances, reduce activity Recent developments – Vdd scaling, VT adjustments Process technology – Silicon-on-Insulator (SOI)

18. 18 Architectural Level Optimization

19. 19 Delay vs. Vdd Reduce the supply voltage to reduce the dynamic power Speed penalty for Vdd reduction

20. 20 Arithmetic Computation Reference datapath Consists of an adder and comparator The power of the reference datapath is given as

21. 21 Parallel Implementation One way to maintain throughput while reducing the supply voltage is to utilize a parallel architecture Two identical adder-comparator datapaths are used, allowing each unit to work at half the original rate while maintaining the original throughput

22. 22 Pipelined Implementation

23. 23 Architecture Based Voltage Scaling ArchitectureVoltageArea (Normalized) Power (Normalized) Simple5 V11 Parallel2.9 V3.40.36 Pipelined2.9 V1.30.39 Pipelined- Parallel 2.0 V3.70.2 Bigger improvement can be achieved by simultaneously exploiting parallelism and pipelining

24. 24 NoC Architectures-System level Parallelism NoC exhibits inherent parallelism

25. 25 Traffic localization Traffic within a cluster – localized traffic

26. 26 Bit energy vs. throughput Traffic Localization reduces energy dissipation Modular architectures help in reducing power Communication aware functional mapping Uniform Spatial Traffic Localized Traffic