1. 1 Course Information Operating System Fall 2006

2. 2 Instructor Information Office: 1N-214 Tel:(718) 982-2841 Email:huo@mail.csi.cuny.edu Webpage: http://www.cs.csi.cuny.edu/~yumei/ Course webpage: http://www.cs.csi.cuny.edu/~yumei/csc718 /csc718Fall06.html

3. 3 Schedule Course Monday, 8:20pm-10:00pm Room: 2N104 Regularly scheduled conference hour 1 hour supplemental independent study Office hour: Monday 7:00pm - 8:00pm Wednesday 1:30pm - 3:30pm or by special appointment

4. 4 Textbook Operating System Concepts by Silberschatz, Galvin, and Gagne, seventh edition, John Wiley & Sons, ISBN 0-471-69466-5.

5. 5 Course Content Overview: Review of computer organization Overview of operating system Process management: Multithreading real-time scheduling synchronization, and concurrency; interaction of concurrent processes; network management and security; Protection; distributed system issues Processes

6. 6 Homework There are four homework assignments. Homeworks will focus on how to use/program with operating system mechanisms. Homework assignments will be assigned during class and also posted on the course Web-page: http://www.cs.csi.cuny.edu/~yumei/csc 718/csc718Fall06.html

7. 7 Homework (cont.) The solution to each homework may include the source code and a report showing the result. The source code must be turned in by email to huo@mail.csi.cuny.edu. huo@mail.csi.cuny.edu The report can be submitted either per email or be handed in a hard-copy at the beginning of the class. Handwritten or typed report will be accepted. Solutions must be readable(especially handwriting!!!), clear, concise and complete.

8. 8 Project One course project Two goals: help you learn more about doing research in general. give you the opportunity to study a particular area of OS in greater detail. Tasks: selecting an problem, designing, implementing, and evaluating a solution, and submitting your report. list of suggestions

9. 9 Grade The exams may test on material covered only in class and on material covered only in the reading assignments. Your grade will be based approximately, as follows. These percentages are tentative and subject to change. 20% - Homeworks 15% - Projects 15% - Midterm Exam #1 15% - Midterm Exam #2 35% - Final Class participation is essential to succeed in this course.

10. 10 Policy DO NOT USE pencils to write down your solutions for the homework, project or exams Check the marks in a homework, project or an exam and report errors promptly. Make sure you report such problems to the instructor within four weeks from receipt but no later than Dec.16, 2005. Homework assignments are due at the start of class on their due date. No later solutions will be taken into consideration! The work you turn in MUST BE your own personal work, composed and written by you. DO NOT OBTAIN YOUR SOLUTION THROUGH THE INTERNET. Collaboration of any kind is NOT allowed in the in-class exams (midterms, and final).

11. 11 Lecture 1: Review of Computer Organization Operating System Fall 2006

12. 12 What is Operating System? Operating system is a program that acts as an intermediary between a user of a computer and the computer hardware. Main GOALS of an OS: To make the computer system convenient to use To use the computer hardware in an efficient manner

13. 13 Four Elements of a Computer System Processor (CPU) Control the operation of the computer and its data processing functions. Main Memory Stores data and programs RAM - random access memory I/O Modules Auxiliary storage like disk drives, tape drives Printers, terminals, monitors System Bus Provides for transfer of data among processors, main memory, and I/O modules

14. 14 Computer Organization CPU PC IR Execution Unit MAR MBR I/O AR I/O BR I/O module … DATA … Instruction … buffer MAIN MEMORY System Bus 0 1 n-1 n-2

15. 15 CPU (Processors) Registers A processor includes a set of registers that provide a level of memory faster than main memory. User-visible Registers Control and Status Registers

16. 16 User-visible Registers Many instructions operate on data sitting on working registers. Since registers are faster than main memory, it is better that data be moved to registers before operating on them. May be referenced by the machine language that the processor executes available to all programs - application programs and system programs. Types of registers: Data registers Address registers For indirect addressing For index register For segment pointer For stack pointer

17. 17 Control and Status Registers Program Controller (PC) – contains the address of an instruction to be fetched Instruction Register (IR) – contains the instruction most recently fetched Memory Address Register (MAR) Memory Buffer Register (MBR) I/O Address Register (I/O AR) I/O Buffer Register (I/O BR) Processor Status Word (PSW) condition codes or flags interrupt enable/disable user/supervisor mode

18. 18 Instruction Cycle Start Fetch next instruction Execute instruction Halt Fetch Cycle Execute Cycle OpcodeAddress of Operand Instruction Format Signmagnitude Integer Format exponentmagnitude Floating point Format Sign

19. 19 Actions of CPU (Types of Instructions) Processor-Memory Data Transfer Processor-I/O Data Transfer Data Processing Arithmetic or logic operation on data Control Alter sequence of execution

20. 20 Interrupts An interruption of the normal sequence of execution Improve processing efficiency Allows the processor to execute other instructions while an I/O operation is in progress

21. 21 Interrupts - Classes of Interrupts Program arithmetic overflow or underflow division by zero attempt to execute an illegal machine instruction reference outside user’s memory space Timer I/O Hardware Failure

22. 22 Interrupts –Interrupt Handler A program that determines nature of the interrupt and performs whatever actions are needed Control is transferred to this program Generally part of the operating system

23. 23 Interrupt Timeline

24. 24 Interrupts and the Instruction Cycle Start Fetch next instruction Execute instruction Fetch Cycle Execute Cycle Interrupts Disabled Check for interrupt and process interrupt Interrupts Enabled

25. 25 Interrupt Cycle Processor checks for interrupts If no interrupts, fetch the next instruction for the current program If an interrupt is pending, suspend execution of the current program, and execute the interrupt handler

26. 26 Program Flow of Control without and with Interrupts User Program WRITE (1) (2) (3) I/O Program I/O Command END (4) (5) No interrupts User Program WRITE (1) (2) (3) I/O Program I/O Command END (4) (5) Interrupt Handler Interrupts

27. 27 Simple Interrupt Processing Device controller or other Hardware generates an interrupt Processor finished execution of current instruction Processor signals acknowledgement of interrupt Processor pushes PSW and PC onto control stack Processor loads new PC value based on interrupt Hardware Save remainder of process state information Process interrupt Restore process state information Restore old PSW and PC Software

28. 28 Multiple Interrupts Two methods: Disable other interrupts while processing one interrupt Assign priorities to different interrupts. Interrupts at higher priority can interrupt lower ones

29. 29 Memory Registers Cache Main memory Electronic disk Magnetic disk Optical disk Magnetic tapes Decreasing cost per bit Increasing capacity Increasing access time Decreasing frequency of access of the memory by the processor volatile nonvolatile

30. 30 Performance of Various Levels of Storage Movement between levels of storage hierarchy can be explicit or implicit

31. 31 Caching Important principle, performed at many levels in a computer (in hardware, operating system, software) Information in use copied from slower to faster storage temporarily Faster storage (cache) checked first to determine if information is there If it is, information used directly from the cache (fast) If not, data copied to cache and used there

32. 32 Cache Invisible to operating system Increase the speed of memory Processor speed is faster than memory speed Contain a portion of main memory CPUCache Main memory Word Transfer Block Transfer

33. 33 Cache Design Cache size Block size Mapping function Determine which cache location the block will occupy Replacement algorithm Determines which block to replace Least-Recently-Used(LRU) algorithm Write policy When the memory write operation takes place Can occur every time block is updated Can occur only when block is replaced

34. 34 I/O Communication Techniques Programmed I/O Interrupt-Driven I/O Direct Memory Access (DMA)

35. 35 I/O Communication Techniques Programmed I/O Interrupt-Driven I/O Direct Memory Access (DMA)

36. 36 Programmed I/O I/O module performs the action, not the processor Sets appropriate bits in the I/O status register No interrupts occur Processor checks status until operation is complete Issue Read command to I/O module Read status of I/O module Check status Read word from I/O module Write word into Main memory Done? Not ready yes Next instruction no CPU->I/O I/O -> CPU Error condition I/O -> CPU CPU->memory

37. 37 I/O Communication Techniques Programmed I/O Interrupt-Driven I/O Direct Memory Access (DMA)

38. 38 Interrupt-Driven I/O Processor is interrupt when I/O module ready to exchange data Processor is free to do other work No needless waiting Consumes a lot of processor time because every word read or written passes through the processor Issue Read command to I/O module Read status of I/O module Check status Read word from I/O module Write word into Main memory Done? ready yes Next instruction no CPU->I/O I/O -> CPU Error condition I/O -> CPU CPU->memory Do something else Interrupt

39. 39 I/O Communication Techniques Programmed I/O Interrupt-Driven I/O Direct Memory Access (DMA)

40. 40 Direct Memory Access Transfer a block of data directly to or from memory An interrupt is sent when the task is complete The processor is only involved at the beginning and end of the transfer Issue Read command to I/O module Read status of DMA module Next instruction CPU->DMA DMA -> CPU Do something else Interrupt

41. 41 End of lecture 1 Thank you!