10/07/2014.

10/07/2014

BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch)
Fast Digital Link Developments for Wire-Scanner and Fast BLM Acquisition Systems B.Dehning, J.Emery, G.Venturini, L.Tore, J.L.Sirvent BI/TB on Fast Optical Links and AWAKE for BI 10/07/2014 BE-BI-BL Jose Luis Sirvent Blasco

Content Wire Scanner Developments: Introduction Long term plans and system design proposal Searching a suitable FPGA GBT implementation on Igloo2 Next Steps Beam Loss Monitor Developments: RadHard Acquisition system under development RadHard Acquisition system project status BE-BI-BL Jose Luis Sirvent Blasco

1. Introduction 1.1 Wire Scanner: Systems and Principle Invasive method for beam transverse profile measurement. System compromises: Wire blow-up (heat) Losses produced Mechanical stresses (Bellows) Calibration procedures Vibrations Types: Rotating Fast Rotating Short/Long Linear Limitations: Tails measurements PMT Saturation effect Adjustments for measurement Dynamic range Long Distances (up to 250m) Total Scanners: 31 Usage in a daily basis at CERN Accelerator Type Quantity SPS Rotating 6 Linear 4 BE-BI-BL Jose Luis Sirvent Blasco 10/07/2014

1. Introduction 1.2 Beam Wire Scanners Upgrade (Specs) Absolute accuracy of beam width determination of about 5 um (~5%) Reduction of play in mechanical system All elements mounted on same axis High accuracy angular position sensor Optical position sensor (Encoder) Overcome bellow limitations Locate all moveable parts in the vacuum Minimize fork and wire deformations: Acceleration profile optimized for low vibrations Mechanical design for minimum shaft and forks deformation New Beam Secondary Shower acquisition System design: Large Dynamic Range measurements without configuration changes Bunch by bunch measurements Low noise for tails (and beam halo) determination BE-BI-BL Jose Luis Sirvent Blasco

1. Introduction 1.3 Analysing long cable impact on measurements BE-BI-BL Jose Luis Sirvent Blasco

2. Long Term plans and system design proposal 2.1 Front-End / Back-End based architecture Usage of the GBT project for Data, Control and Timing transmission FE <->BE GBT 4.8Gbps: Enough bandwidth for our application (80 bits each 25ns) and FEC for possible data SEU correction. Beam Synchronous measurements: Timing sent through the GBT link, 40Mhz acquisition synchronized with the beam (SPS & LHC) Two serious candidates as readout ASIC for pCVD diamond Detector: ICECAL (LHCb) : Low noise analog gated Integrator (12 bits Dynamic Range) QIE10 (CMS) : Charge Integrator and Encoder (17 bits Dynamic Range) We’ll design for tunnel radiation levels: 100Gy/year  up to 1KGy (10 years) BE-BI-BL Jose Luis Sirvent Blasco

2. Long Term plans and system design proposal 2.1 Front-End / Back-End based architecture Radiation Specifications of front-end components: QIE10: Technology: 0.35 um AMS SiGe By Specs survive at least up to 1KGy Radiation tests performed on september 2013 ASIC Worked at least up to 400Gy and critical failure at 3.3KGy ICECAL: Technology: 0.35um AMS SiGe GBTx: Technology: 130 nm CMOS commercial RadTol By specs specked total dose up to 1MGy VTRx: By specs specked total dose up to 500KGy Radiation qualified LD & PD Now completely available DC/DC Converter: Based on Cern’s DC/DC Module (FEAST2) Technology: 0.35um CMOS Total TID > 1Mgy Usage of the GBT project for Data, Control and Timing transmission FE <->BE GBT 4.8Gbps: Enough bandwidth for our application (80 bits each 25ns) and FEC for possible data SEU correction. Beam Synchronous measurements: Timing sended through the GBT link, 40Mhz acquisition synchronized with the beam (SPS & LHC) Two serious candidates as readout ASIC for pCVD diamond Detector: ICECAL (LHCb) : Low noise analog gated Integrator (12 bits Dynamic Range QIE10 (CMS) : Charge Integrator and Encoder (17 bits Dynamic Range) Designed for tunnel radiation levels: 100Gy/year  up to 1KGy (10 years) BE-BI-BL Jose Luis Sirvent Blasco

2. Long Term plans and system design proposal 2.2 QIE10 Compact Front-End in detail BE-BI-BL Jose Luis Sirvent Blasco

2. Long Term plans and system design proposal 2.2 QIE10 Compact Front-End in detail (Possible Level Converters) Level Translators Functionality Reference Ch. IC needed Provider Vcc Speed TID Qualified by: SLVS  CMOS (GBTxQIE10 Controls) MAX9179 4 3 Maxim 3.3V 400Mbps -- DS90C032QML TI <800Mbps 1KGy DS90LV048ATM 0.7kGy* ATLAS HXLVDSR Honeywell 100Mbps 3KGy SN55LVDS32-SP RHFLVDS32A ST SLVS  LVDS (GBTxQIE10 Reset) MAX9376 2 1 2Gbps UT54LVDM328 8 Aeroflex 3KGy** RHFLVDS228A CMOS  LVDS (QIE10 Controls  GBTx) MAX9112 500Mbps DS90C031QML DS90LV047ATM <400Mbps 0.7KGy* HXLVDSD UT54LVDM055LV SN55LVDS31-SP RHFLVDS31A *Tullio Grassi’s list: **LHCb COST rad Hard: ++ European Space Components Information Exchange System: BE-BI-BL Jose Luis Sirvent Blasco

2. Long Term plans and system design proposal 2.3 Usage of the GBTx ASIC (GBT Project) Not yet available for users and very few samples!! Alternative for Front-End optical Link driver needed… We decided to GBTx Emulation through FPGA as temporal or back-up solution (when ASIC available we could decide). *Information from Paulo Moreira slides BE-BI-BL Jose Luis Sirvent Blasco 10/07/2014

2. Long Term plans and system design proposal 2.4 Our approach in the design consist on Dev. Boards Motivation: The final proof-of-concept can be evaluated by using this assembly. The Igloo2 in this case could be configured to act purely as a GBTx asic, this way the system could be suitable to work with Igloo2 or GBTx in case of change for final board. Tasks: The system has to be configured to work in a complete assembly by using the knowledge from the previous tasks. The set-up should be done in a way to make possible Igloo2-> GBTx migration. Final tests and evaluation has to be done in with the assembly for system demonstration At this point a decision could be done regarding the FPGA usage or the development of a compact board with GBTx. BE-BI-BL Jose Luis Sirvent Blasco

3. Searching a suitable FPGA 3.1 Why we selected Microsemi Igloo2?
Flash Based FPGA with “SEU Immune” configuration memory New FPGA in 65nm technology, and first Flash-based that includes 5Gbps Positive experiences with previous family in other experiments ProASIC3. FPGA Technology Comparison Technology Flash-Based SRAM Vendors Microsemi Actel, Xilinx… Families ProASIC3, SmartFussion, Igloo Virtex, Cyclone, Kintex, Spartan… Configuration Tolerant to SEUs Yes No Configuration SEU Mitigation Techniques TMR Scrubbing Typical TID Limits 20-40 kRad (ProASIC3) 100s kRad (maybe IG2)** 100s kRad* Comments Reprogramming improves performance. Configuration memory easily corrupted. *High Dependency of mitigation techniques performance **Still under characterization BE-BI-BL Jose Luis Sirvent Blasco 10/07/2014

4. GBT implementation on Igloo2 4.1 GBT-FPGA Project (Some information and resources) Part of the Radiation Hard Optical Link Project: Development of firmware for Back-ends to communicate with GBTx – based front-ends and GBTx Emulation. Coverage of 8b/10b, Wide-Bus and GBT mode (Reed-Solomon Based) Public SharePoint: Public SVN Releases : Mailing List: Contacts for support: , Last news: Standard (STD)  Data Readout(DAQ) Low and Deterministic latency (LATOP) ) FE control & Time, Trigger and control (TTC) Support & code available for (Dev. Kits): Xilinx Virtex 6 / 7 & Kinex 7 Altera Cyclone V & Statrix V BE-BI-BL Jose Luis Sirvent Blasco

4. GBT implementation on Igloo2 4.3 Migration from Virtex 6 to Igloo2
Based on the STD release the code was adapted for this new FPGA (Satisfactory results) When the LATOP version was released the code was modified and the different clock domains adjusted. LATOP & STD Versions successfully implemented on Igloo2 (but some more test were required) BE-BI-BL Jose Luis Sirvent Blasco

4. GBT implementation on Igloo2 4.5 Tests Set-Up
The modified version of GBT_FPGA for Igloo2 was finally implemented 2.5Gbps & 5Gbps. The GBT Firmware was finally organized & commented properly, including an error counter and Boards auto-detection. The Console Application was modified and re-structured to include the error counter. Needed to verify timing details to check if we can recover the LHC clock on the front-end system. (Study the recovered Clk phase, link latency and ref frequency tolerance TX  RX). BE-BI-BL Jose Luis Sirvent Blasco

4. GBT implementation on Igloo2 4.6 Clock Recovery 5Gbps), phase variation. FRAME_TX_CLK (Board 1) FRAME_RX_CLK (Board 2) These are the clocks after the TX & RX PLLs, based on EPCS_ TX & RX _CLK Initial observations on STD Version: Phase variation is random. This would be our CLK for acquisition electronics The PLL can lock on any of the 6 rising edges of RX_WORD_CLK. Possible to optimize phase variations adjusting the PLL CLK phase on based on RX_HEADER_FLAG To be seen if only adjusting Frame_Clk the link provides deterministic latency. BE-BI-BL Jose Luis Sirvent Blasco

4. GBT implementation on Igloo2 4.6 Clock Recovery 5Gbps), phase variation. STD PLL Ref_CLK: EPCS_RX_CLK Clock non aligned 6 Possible rising edges to lock 20 possible delays (0-4 ns) 120 possible phases Random clock phase relationship 100% uncertainty PLL Ref_CLK: RX_HEADER_FLAG Clock aligned to Header_Flag 20 possible delays (0-4 ns) Phase relationship defined by Bitslip_Number 16% uncertainty LATOP PLL Ref_CLK: RX_HEADER_FLAG + Phase alignment Clock aligned to Header_Flag Delay defined by BITSLIP_NUMBER compensated Use of PLL delay lines (steps of 100ps) 20 possible delays ( ns) Clocks phase more stable 5.58% uncertainty BE-BI-BL Jose Luis Sirvent Blasco

4. GBT implementation on Igloo2 4.7 Link latency observing tx & rx match flags TX_MATCH_FLAG (Board 1) RX_MATCH_FLAG (Board 2) These are flags that goes to 1 when certain frame is detected Initial observations on STD Version: As expected the latency is not deterministic, with a pseudorandom behaviour. The Phase differences on the Word & Frame Clocks are the responsible of this delay variation. If we are able to align the clocks properly the link delay would be “more stable”. Random Variation Around 315ns BE-BI-BL Jose Luis Sirvent Blasco

4. GBT implementation on Igloo2 4.7 Link latency observing tx & rx match flags STD PLL Ref_CLK: EPCS_RX_CLK Using Gearbox_LATOP Link delay influenced by: FRAME CLK rising edge BITSLIP_Number Pseudo-random latency (+- ~25ns) PLL Ref_CLK: RX_HEADER_FLAG Using Gearbox_STD Link delay influenced by: Elasticity of Gearbox_STD BITSLIP_Number Clear dependency of Bitslip_number (FRAME_CLK delay) Delay Variation  3.8ns LATOP PLL Ref_CLK: RX_HEADER_FLAG + Delay compensation Using Gearbox_LATOP Not reduced to 0 – 200ps ?? Clock Frequency variations? Delay Variation  1.4ns BE-BI-BL Jose Luis Sirvent Blasco

4. GBT implementation on Igloo2 4.8 LHC Clock transmission to the Front-End (Ref_CLK Differences) To verify by testing: Will It be possible to work with such difference on the REF_CLKs? Do we recover the correct EPCS_RX_CLK when the REF_CLK are different? Which are the difference limits on REF_CLKs? If the TX REF_CLK varies during transmission the link will suffer errors? BE-BI-BL Jose Luis Sirvent Blasco

4. GBT implementation on Igloo2 4.8 LHC Clock transmission to the Front-End (Ref_CLK Differences) Accelerators during Ramp: LHC operations require a clock tolerance of ~2.5 ppm SPS operations require a clock tolerance of ~600ppm We’ll play with Ref_CLK’s around 125Mhz A safe region was found for 2.5 & 5Gbps Board 1  Mhz Board 2  ± 0.5 Mhz Difference  0.8%  8000 ppm >> 600 ppm We met the specs Board 2 Variable Ref_CLK 123.5 – Mhz Board 1 Local Ref_CLK 125Mhz BE-BI-BL Jose Luis Sirvent Blasco

4. GBT implementation on Igloo2 4.9 Optical Link Details summary
Integrated Igloo2 5Gb/s For 4.8Gb/s needed reference at 120MHz GBT protocol in frames of 120 bits: 4 bits header + 84 bits payload + 32 bits FEC Used Bandwidth: ICECAL Board  ~30% // QIE10 Board  ~20% Each frame is sent every 25ns synchronized with bunch crossing frequency. Front-End will use the recovered clock in reception for acquisition and transmission. Back-End is continuously sending “dummy” data to maintain synchronization. LATOP version used for fixed latency with an small variation around ~1.4ns. GBT-on-Igloo2 has shown satisfactory results but many things need to be tested: Recovered CLK quality is good enough for acquisition electronics (Jitter)? Need to test SERDES configuration were the recovered clock is used as TX clock. Verify if recovered clock follows well LHC & SPS Ramp variations (needed frequency sweep) How to include in data Front-End diagnostics information. Need to specify Front-End control protocol through GBT link. The GBT optical link for Igloo2 is almost ready BE-BI-BL Jose Luis Sirvent Blasco

4. GBT implementation on Igloo This has become a collaborative project People and experiments interested on GBT on Igloo2: Tullio Grassi (+), Tom O’baron(+)(++), Frédéric Machefert(*)(++), Chistophe Beigbeder (*)(++) , Us (**). Many others are wellcome!! Just contact me ! (+)CMS experiment: Compact Muon Solenoid Experiment (++)LHCb collaboration: Large Hadron Collider beauty collaboration (*)LAL : Laboratoire de l´Accélérateur Linéaire (**)Beam Instrumentation Group Why such interest? : Igloo2 Flash based technology (“SEU Inmune Fabric”) with 5G SERDES. Good results obtained with previous family (ProAsic3). Applications where high speed data transfer is needed in areas with radiation. Promising irradiation results (more test will come more soon). BE-BI-BL Jose Luis Sirvent Blasco

4. GBT implementation on Igloo This has become a collaborative project (Code availability) First release STD version available for download (09/06/2014) : In DropBox: In SVN (Use Tortoise or other SVN client): Diamond detector Readout Electronics/GBT_On_Igloo2/Firmware/GBT_FPGA_Igloo2/STD What is provided: Libero 11.3 Project with GBT_on_Igloo2 code: (2014_06_09_GBT_On_Igloo2_M2GL_EVAL_KIT.rar) Features: GBT Protocol (STD Version) on Igloo2 with UART communication through USB port. Constraints are not always met, so care must be taken when new changes are performed analysing timing reports. All the necessary VHDL files are in : GBT_On_Igloo2_M2GL_EVAL_KIT\hdl Programming file (stp) available in : GBT_On_Igloo2_M2GL_EVAL_KIT\designer\GBT_On_Igloo2_M2GL_EVAL_KIT\export In case of trouble, just let me know!! there are many things to improve. Console Application UART_APP_V3.0: (2014_06_09_UART_APP_V3.0.rar) Features: Controls the workflow of the GBT implementation on Igloo2 and checks different signal values and parameters of the link (RX_BITSLIP_NUMBER, Error number…), Boards Auto-Detection. Microsoft Visual Studio 2008 Project: UART_APP_V3.0\UART_APP.sln Executable File: UART_APP_V3.0\Release\UART_APP.exe Readme File: (2014_06_09_Readme.pdf) Features: Short guide to implement the design on the Dev.Kit and run the application BE-BI-BL Jose Luis Sirvent Blasco

5. Next Steps 5.1 ICECAL_V2 Front-End Acquisition Board for Secondaries (I-FABS) Characteristics: Modified version from Icecal_V2 Test board used by the ASIC designers (E. Picatoste, D. Gascon. University of Barcelona) Direct connection to Igloo2 Dev. Kit Used for ICECAL performance testing (Laboratory) and front-end proof-of-concept (Tunnel) BE-BI-BL Jose Luis Sirvent Blasco

5. Next Steps 5.2 I-FABS Demonstrator set-up
Placed in the SPS tunnel It will be used for: Systems measurement quality comparison (Old system VS New system) Optical Link performance test for long distances Igloo2 Firmware improvements (Possible Front-End diagnostics on GBT frame) First step for the integration of the new system on the wire scanner architecture. QIE10 board has to be developed in a similar way for testing Board placed ~1.5m away from the beam pipe. TID ~ 0.1 kGy/y (PS) BE-BI-BL Jose Luis Sirvent Blasco

5. Next Steps 5.3 I-FABS Routing Status so far…
BE-BI-BL Jose Luis Sirvent Blasco

5. Next Steps 5.3 I-FABS Radiation Considerations
Voltage Regulators: TL1963-KTT  Qualified up to 1KGy by PSI for MOPOS [1,3] Analogue to Digital Converter : ADS5272  Total TID 88KGy for ATLAS, tested at IUCF / LANSCE WNR [2] Differential operationals (Gen. Inputs): THS4521  Qualified up to 1KGy by PSI for MOPOS [1,3] Readout ASIC: ICECAL_V2  RadHard development Programmable Delay Lines: 3D3418  Total TID 5Krad [4] Rail-to-Rail Comparators LT1711  Not Qualified (ICECAL Clock conditioning) LVDS _CMOS Receiver DS90LV048A  Tested with 60MeV p beam up. Qualified up to TID = 0.7KGy [6] (ADC Clock Conditioning) Bias Operationals (I_BIAS Circuit) OPA602  Tested up to 2.7KGy (Neutrons), but not qualified [5] Dual Current Source / Current Sink REF200  Not Qualified There are some additional components to add to this list [1] C. Deplano∗, J. Albertone, T. Bogey, J. L. Gonzalez, J. J. Savioz RADIATION RESISTANCE TESTING OF COMMERCIAL COMPONENTS FOR THE NEW SPS BEAM POSITION MEASUREMENT SYSTEM. CERN, Geneva, Switzerland [2] Helio TAKAI. Characterization of COTS ADC radiation properties for ATLAS LAr calorimeter readout upgrade. TWEPP13, September 2013 [3] J.Albertone, T.Bogey, C.Delplano, J.L. Gonzalez. Logarithmic Amplifiers, ADC Drivers and Voltage Regulators: Radiation Test Report at PSI-PIF. 2013 [4] J. Gu. EMU DAQ MotherBoard. ERS, CERN Nov [5] F. J. Franco, Y. Zong, Juan Casas-Cubillos, M. A. Rodríguez-Ruiz, and J. A. Agapito. Neutron Effects on Short Circuit Currents of Op Amps and Consequences. IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 52, NO. 5, OCTOBER 2005 [6] G. Di Mattia Thesis. Test del funzionamento e della resistenza alle radiazioni dell’elettronica per il trigger di primo livello dell’esperimento ATLAS. Università degli Studi di Roma “La Sapienza” BE-BI-BL Jose Luis Sirvent Blasco

6. Conclusions Beam Wire Scanner (BWS): BWS Readout Electronics will be upgraded with Front-End / Back-End architecture. The GBT optical link will be used for Data, Timing and Control. For long term the GBTx ASIC plans to be used. Due to availability our back-up, or possible final, solution is emulation. GBT Implementation in Igloo2 is ready (STD & LATOP). Performed tests are showing a promising performance. When the link was established no errors on data where found. Beam synchronous signal (40Mhz Clock) can be recovered in the front-end properly (preliminary results). The link works well for different Ref_Frequencies in FE/BE (bigger than LHC & SPS CLKvariations). The first Analog Front-End board (ICECAL) is being developed for evaluation. Beam Loss Monitor (BLM): BLM ASIC Version 1 successfully tested This is a large scale and critical system, so Front-Ends with TMR and redundant optical links GBTx emulation through FPGA for BLM ASIC acquisition chain tests BE-BI-BL Jose Luis Sirvent Blasco

4. GBT implementation on Igloo2 4.4 Latency Optimized Clock management on Igloo2 BE-BI-BL Jose Luis Sirvent Blasco

Back-up Slides Igloo2 Irradiation reports:
Univ. of Minnesota [1] Fluence runs 1e11 and 2e12 p/cm2 Registers no TMR  Cross-Section = 2e-6 cm2 Registers TMR  Cross-Section < 5e-7 cm2 Combinatorial logic  Cross-Section < 1.5e-4 cm2 PLL SEU 400 observed over 10e11 p/cm2  Cross Section = 4e-9 cm2 No SEU seen on TMR shift register No SET seen TID ~100kRad (2e12p) “The failure likely because too much current was drawn, although further testing is needed to determine how much current the chip can handle” Future Electronics [2] Non Destructive SEL Total Fluence 1.07e9 ant LET levels up to 30.86MeV-cm2/mg. SEL LET 100 deg > 22.5MeV-cm2/mg (Proton/Neutron Inmune SEL) Non destructive SEL found at LET = 24MeV-cm2/mg Configuration memory SEU: No configuration upsets detected at fluence 2.83e9 Heavy ions. Data SEU: Flip Flops (Total Fluence = 4.35e11 n/cm2) : 1.13e feet / 218e3 FIT @ ground level per million FF Large Ram Blocks (Total Fluence = 1.7e11 n/cm2): e feet / FIT @ ground per million bits. Micro SRAM Blocks (Total Fluence = 1.7e11 n/cm2): 9.04e / FIT @ ground per million bits. Single Event Functional Interrupts (SEFI): MSS (Total Fluence = 7.11e9 n/cm2)  0 SEFIs Found PLL (Total Fluence = 3.29e10 n/cm2)  0 SEFIs Found Microsemi Corporation [3] TID resistance ~ kRad  “Icca increase due to isolation Flash Switch, gradually turning on by ionizing radiation.” [1] A. Finkel, J. Mans, J. Turkewitz, Radiation Testing of an Igloo2 Fpga. University of Minesota. January 14th, 2014 [2] Future Electronics. Microsemi Corporation Igloo2 and SmartFusion2 65nm Commercial Flash FPGAs Interim Summary of Radiation Test Results. June 20, 2014. [3] JJ Wang et al. Using Microsemi Flash-Based FPGA in radiation Environment. Workshop on FPGAs for High Energy Physics BE-BI-BL Jose Luis Sirvent Blasco

Back-up Slides QIE10 Architecture
QIE10 Characteristics and functionality(*): Rad-Hard Charge-Integrating ASIC (25ns) Fast, Wide dynamic range, Dead-Timeless ADC (Latency: only 4x25ns) Very High dynamic range: 3.2fC  340pC (Fits well our initial estimations!!) LSB 3.2fC (Almost MIP for pCVD) Non linear charge digitalization scheme: 6 bit FACD mantissa + 2 Exp (4 Ranges) TDC capability: Produces TDC info based on the Rising/falling edge of pulse (2 configurable 8bits thresshold levels) Inputs: Reset (CLK Alignment) Charge signal (from pCVD) CLK Programmable stuff ( Thressholds, Pedestrials…) Outputs: Q : Charge Integral T1: Arrival time (500ps resolution) T2: Falling time (500ps resolution) QIE10p4 Already available! QIE10p5 soon (maybe also available) * “CMS Specifications Document for the QIE10 ASIC. 2010” BE-BI-BL Jose Luis Sirvent Blasco 37

Back-up Slides ICECAL Architecture
BE-BI-BL Jose Luis Sirvent Blasco

Back-up Slides GBT-FPGA Project (Latency Optimized Release with clock alignment) GBT-FPGA One unified core for multiple users. Manoel Barros Marin, PH/ESE/BE Students-Fellows seminar (05/02/2014). BE-BI-BL Jose Luis Sirvent Blasco

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