1. TCAD Simulation for SOI Pixel Detector
October 31, 2007
IEEE-NSS, Honolulu, Hawaii, USA
Hirokazu Hayashi, Hirotaka Komatsubara (Oki Elec. Ind. Co.),
Yasuo Arai, Masashi Hazumi (KEK),
Yuji Saegusa (TIT)
for the SOIPIX group

2. SOIPIX collaborators
KEK Detector Technology Project : [SOIPIX Group]
Y. Arai*, M. Hazumi, Y. Ikegami, T. Kohriki, O. Tajima, S. Terada, T. Tsuboyama, Y. Unno, H. Ushiroda, H. IkedaA, K. HaraB, H. MiyakeB,
H. IshinoC, Y. SaegusaC,
T. KawasakiD, E. MartinE, G. VarnerE, H. TajimaF, K. FukudaG, H. HayashiG, H. KomatsubaraG, J. IdaG , M. OhnoG
KEK、JAXAA, U. TsukubaB, TITC, Niigata U.D, U. HawaiiE, SLACF,
OKI Elec. Ind. Co.G
(*)—contact person
2006/10/31
M. Hazumi (KEK)

3. Overview TCAD ENEXSS (Environment for NExt Simulation System)
TCAD = Technology CAD
ENEXSS (Environment for NExt Simulation System)
Developed by Selete (Semiconductor Leading Edge Technologies) ( )
Full 3D process/device simulation !
Commercially available from TCAD-International ( )
Real
LSI Manufacturing
Specifications
Virtual
Fast 
Deeper
understanding 
Function design
TCAD
Process
simulation
Device
Back gate effect
Circuit-sensor crosstalk
Implantation parameters
Guard ring design
Pixel layout
Topics covered in this talk
Logic design
Process data
Circuit design
Device data
Layout design
~3mon. 
Characterization
Mask fabrication
Prototyping
Device production
2006/10/31
M. Hazumi (KEK)

4. Back gate effect ENEXSS
Substrate voltage acts as Back Gate, and changes transistor threshold.
TCAD
VB (V)
Threshold voltage (V)
Back bias (V)
ENEXSS TCAD
ENEXSS
Measurement
2006/10/31
M. Hazumi (KEK)

5. Back gate effect: mitigation with p+ implants
MPW06
NMOS
distance (D) (40 – 2 mm)
BOX (200nm) 
Bulk: N- (~700ohm cm, 6 x 1012 cm-3)
(5 mm wide P+, 1 x 1020 cm-3) 
350mm
p+ implant (0V) for I/O buffer
ENEXSS D
Measurement
(10MHz clock)
Back bias
= 40V
Out In
2006/10/31
M. Hazumi (KEK)
Back bias
Much improved !

6. Circuit-sensor crosstalk
Signals in the circuitry very close to the sensor
may inject noise to the sensor.
ENEXSS
Input
OK for charge-integrated device.
Need some care for other cases
2006/10/31
M. Hazumi (KEK)

7. Implantation parameters
Find the best ion and beam energy to achieve the
highest breakdown voltage (vital important for full depletion)
Example 1)
Ion #1
Ion #2
2mm
Vbreak = +88.5V
= V
Example 2)
“Deeper” implantation mitigates impact ionization (II) and results in a higher breakdown voltage.
~20% improvement expected by doing both.
ENEXSS
2006/10/31
M. Hazumi (KEK)

8. Test structure (strip sensor)
MPW06
Standard
New
Measurement
~20% improvement observed
2006/10/31
M. Hazumi (KEK)

9. Guard ring design ENEXSS ...
Better guard ring design also helpful to improve breakdown voltage.
ENEXSS
Pixels
I/O
VSS Ring
Bias Ring
Guard Ring
SOI pixel detector
...
MPW06
1 guard + 1bias
MPW06
2 guards + 1bias
20V at the back side
E [V/cm]
1 guard ring (MPW06)
2 guard rings (next
submission)
40000
20000
d [um] 40 30 10 20
Bias Ring edge
Bias
Guard
60000
80000
100000
An additional guard ring
is effective to reduce
the electric field concentration.
2006/10/31
M. Hazumi (KEK)

10. Pixel layout B A
For digital readout, charge sharing curve at the cell boundary should be as steep as possible.
cell A
cell B
Note that in our design there are
4 p+ implants in one cell connected
in the readout.
MIP-like charge injection with TCAD
for the 3 layouts shown below
ENEXSS
+:①
+:②　　
+:③ x
[mm] 15 5 ① 20 10 ② ③ 4 3 17 16
Narrower gap b/w
two cells (③)
slightly better. x 2
2006/10/31
M. Hazumi (KEK)

11. Summary
Back gate effect largely mitigated with additional p+ implants near the circuitry.
Circuit-sensor crosstalk is not an issue for digital pixel readout with charge integration.
Higher breakdown voltage with improved implantation parameters (~20% achieved)
Additional guard ring can reduce the electric field by factor ~2.
Implantation gap b/w two cells should be minimized (present design seems close to the best)
Good prospects for thinned fully-depleted SOI pixel !
2006/10/31
M. Hazumi (KEK)