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IKI10201 08-Register-transfer Design
Bobby Nazief Semester-I The materials on these slides are adopted from: Prof. Daniel Gajski’s transparency for Principles of Digital Design.
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Road Map Logic Gates & Flip-flops Boolean Algebra 3 3
Finite-State Machines 6 Logic Design Techniques 4 Sequential Design Techniques 6 Combinatorial Components Storage Components Binary Systems & Data Represent. 2 5 7 8 Generalized FSM 8 Register-Transfer Design Processor Components 9
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Review: Simple datapath
Datapath are used for temporary variable storage & operation execution storage register file, accumulator operation execution ALU Datapath has 2 types of input/output: data words (input/output): 8, 16, 32, or 64 bits wide control signals: input: control words output: status signals
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Review: Control unit Control unit is a sequential circuit that controls datapath’s operations it receives computer’s instructions (our programs) and status signals (from Datapath) as input it generates the control words (for Datapath) and other control outputs
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Design model: high-level block diagram
Processors & ASICs (Application-Specific Integrated Circuit) consist of 2 components: control unit datapath
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Design model: register-transfer-level block diagram
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Example: one’s counter specification
Basic algorithm: Data = Inport Ocount = 0 Mask = 1 while Data 0 repeat Temp = Data AND Mask Ocount = Ocount + Temp Data = Data >> 1 end while Outport = Ocount
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FSM with Datapath (FSMD)
FSM: Quintuple <S,I,O,f,h> S = Q1 x Q2 x ... x Qm I = A1 x A2 x ... x Ak O = Y1 x Y2 x ... x Yn f: S x I S h: S x I O FSMD = FSM, extended with: set of variables: V = V1 x V2 x ... x Vq I = IC x ID O = OC x OD next state functions: fC: S x IC x STAT S fD: S x V x ID V output functions: hC: S x IC x STAT OC hD: S x V x ID OD
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State & output table Control Unit Datapath
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State & output table w/ variable assignments
Simpler expressions
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State-action table This table can be used to:
construct state diagram for the control unit synthesize next-state & output logic define the datapath components & their connections Output = Z
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Algorithmic-State-Machine (ASM) chart
ASM charts: an alternative graphic form for specifying FSMDs may suit humans better as they explicitly show the paths from one state to another ASM chart consists of: state box decision box conditional output box ASM block
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ASM’s chart for one’s counter
One’s counter ASM chart using a standard datapath:
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ASM’s charts for one’s counter (custom design)
state-based chart input-based chart The use of custom datapath may result in fewer components and interconnections. Examples (in the case of one’s counter design): state-based (Moore) chart requires 6 states (all variable assignments must be executed unconditionally) input-based (Mealy) design requires 4 states (variable assignments may be executed conditionally)
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State-action table & logic equations (state-based)
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One’s counter circuit (state-based)
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State-action table & logic equations (input-based)
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One’s counter circuit (input-based)
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