1. L1 Pixel Trigger: Is 20 us Latency Achievable? David Christian Fermilab April 29, 2015

2. Background Pixel Region of Interest (ROI) electron trigger, seeded by Ecal, suggested years ago by Roland Horisberger*. – ROI would be large in z; readout bandwidth a problem??? Fast forward to 2014: – Studies of Ecal seeded pixel electron trigger presented at trigger/trigger workshop (9/2014@FNAL) (A. Savoy Navarro); also B tagging (C-S Moon) – Studies of Outer tracker electron triggers also presented; very impressive… pixels not needed at L1? – Possibility of pixel ROI seeded by tracks also discussed (for H(bb), VBF H, Z(nu,nubar)H(bb),…) Track trigger latency = 12.5us A pixel L1 ROI seeded by tracks would require ~20 us L1 latency. ROI would be tiny (< 1 ROC); no problem with readout bandwidth. * (I know I have Roland’s slides somewhere, but can’t find them & so can’t provide a proper reference) April 29, 2015From US CMS Upgrade Meeting at Caltech

3. Pixel ROC with 20us latency? Q: Could the phase-2 pixel ROC provide enough storage for a 20us L1 latency? A: The quick answer is yes. The somewhat longer answer follows. April 29, 2015From US CMS Upgrade Meeting at Caltech

4. Latency buffer in the periphery All flavors of PSI46 buffer data in the chip periphery. – Buffer size required is only very slightly more than the size required for the average occupancy in the highest rate location (because the number of hits stored is large and the fluctuations are random). This type of buffer must increase in size linearly with L1 latency. – It’s also quite efficient  L1 buffer is fairly small, especially if scaled from.25u to 65nm (or even 130nm).  20us L1 buffer would not be a problem. April 29, 2015From US CMS Upgrade Meeting at Caltech

5. The problem with the periphery If the latency buffer is in the periphery, all hit data must be moved from the pixel array to the periphery. – At high rate, with high occupancy, the rate that data can be moved from the array to the periphery becomes a limiting factor. – This is the most problematic aspect of the PSI46 architecture for the inner layer(s) of the phase-2 pixel detector. April 29, 2015From US CMS Upgrade Meeting at Caltech

6. The way to high rate capability If the L1 latency buffer is distributed throughout the pixel array (vastly increasing the number of parallel paths from FEs to latency buffer), then this rate constraint is lifted. April 29, 2015From US CMS Upgrade Meeting at Caltech FEI4 (From Malte Blackhaus, arXiv:1202.3592v1)

7. Distributed L1 buffer - disadvantages If the size of the pixel region served by a single buffer is small, then occupancy fluctuations will be large. – The buffers must be (dramatically) oversized. However, the buffer size does not depend linearly on the latency. – Even a short latency requires a (comparatively) large buffer. – Longer latency provides time for fluctuations to average out, so the required buffer size increases slowly. April 29, 2015From US CMS Upgrade Meeting at Caltech

8. Distributed L1 buffer: example The only example that is easy to evaluate is the case of a separate buffer in every pixel. – In this case, the size requirement is given by average hit rate/area/crossing, a data-loss spec, and Poisson statistics. The draft CMS Phase-2 pixel spec is for less than 0.1% data loss in the pixel ROC. The draft spec assumes 2 GHz of pixel hits/cm 2 (500 MHz/cm 2 tracks) in the hottest regions of the pixel detector and 50u x 50u (or 25u x 100u) pixels  0.05 hits/pixel/crossing. April 29, 2015From US CMS Upgrade Meeting at Caltech

9. L1 delay/pixel example, continued L1 delayAve # of hits# of buffer locations required for <0.1% data loss. 5 us0.254 10 us0.55 20 us1.06 April 29, 2015From US CMS Upgrade Meeting at Caltech If the L1 latency buffer is shared by a group of pixels, then a detailed simulation must be performed to determine the required size of the buffer.

10. L1 buffer shared by larger pixel region Study by Elia Conti (J. Christiansen) – assumes 20us L1 latency – 20% - 40% gain by sharing latency buffer among a group of pixels. – Also allows sharing of other logic (potentially more real estate gain). April 29, 2015From US CMS Upgrade Meeting at Caltech

11. L1 buffer size limit? Q:Is there enough space in a 25u x 100u pixel for a L1 buffer given 20us latency? A: Probably so. – FE prototypes take ~25u x 50u (50% of pixel). – If I assume 6 hits @ 14 bits/hit (10 bit BCO + 4 ADC), & 4 u 2 /bit (scaled from prototype rad tolerant SRAM bit), then area required = 256 u 2 = 10% of pixel area. – This can be reduced somewhat by using a larger pixel region. – L1 ROI trigger would also require more complex R/O logic, some of which would need to be distributed. Almost for sure doable. Needs to be included in design specs (currently listed as an option in the draft CMS spec). April 29, 2015From US CMS Upgrade Meeting at Caltech