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ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices Adders, subtractors, ALUs.

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Presentation on theme: "ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices Adders, subtractors, ALUs."— Presentation transcript:

1 ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices Adders, subtractors, ALUs

2 Prev… XOR (2-level, 3-level)  Equivalent symbols  XNOR Parity Circuits (Odd, even)  Daisy chain  Tree

3 Adders/Subtractors Half Adder Full Adder Ripple Adder Full Subtractor Ripple Subtractor Adder/ Subtractor Circuit

4 Half Adder: adds two 1-bit operands Truth table : X Y HS=(X+Y) CO 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 Y X H S CO

5 Full Adders: provide for carries between bit positions Basic building block is “full adder”  1-bit-wide adder, produces sum and carry outputs Truth table:

6 Full Adders: provide for carries between bit positions Basic building block is “full adder”  1-bit-wide adder, produces sum and carry outputs Truth table: XYCinSCout 00000 00110 01010 01101 10010 10101 11001 11111

7 Full Adders: provide for carries between bit positions Basic building block is “full adder”  1-bit-wide adder, produces sum and carry outputs Truth table: XYCinSCout 00000 00110 01010 01101 10010 10101 11001 11111 S is 1 if an odd number of inputs are 1. COUT is 1 if two or more of the inputs are 1. Recall: Table 2-3, pp32

8 Full-adder circuit

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11 Ripple adder Speed limited by carry chain Faster adders eliminate or limit carry chain  2-level AND-OR logic ==> 2 n product terms  3 or 4 levels of logic, carry look-ahead

12 74x283 4-bit adder Uses carry look-ahead internally

13 16-bit group-ripple adder

14 Subtraction Subtraction is the same as addition of the two’s complement. The two’s complement is the bit-by-bit complement plus 1. Therefore, X – Y = X + Y’ + 1

15 Full Subtractor = full adder, almost X,Y are n-bit unsigned binary numbers Addition : S = X + Y Subtraction : D = X - Y = X + (-Y) = = X+ (negative Y, in two’s complement) = X+ (Complement of all bits of Y) + 1 = X+ Y’+ 1

16 Full Subtractor = full adder, almost X,Y are n-bit unsigned binary numbers Addition : S = X + Y Subtraction : D = X - Y = X + (-Y) = = X+ (negative Y, in two’s complement) = X+ (Complement of all bits of Y) + 1 = X+ Y’+ 1

17 Using Adder as a Subtractor Ripple Adder can be used as a Subtractor by inverting Y and setting the initial carry ( CIN ) to 1

18 Using Adder as a Subtractor Ripple Adder can be used as a Subtractor by inverting Y and setting the initial carry ( CIN ) to 1

19 MSI Arithmetic Logic Units (ALU ) ALU performs Arithmetic and Logical Functions - A, B : 4 bits inputs - S3,S2,S1,S0 : Function select - M=0 : Arithmetic operations +=Plus, - = Minus M=1 : Logical operations : += OR,. =AND Example : Inputs Functions S3 S2 S1 S0 M=0 M=1 0 0 0 0 F= A-1+CIN F=A’ 0 1 1 0 F= A-B-1+CIN F=A XOR B’ 1 0 0 1 F= A+B+CIN F=A XOR B 1 0 1 1 F=(A OR B)+ CIN F=A+B 1 1 0 0 F= A+A+CIN F= 0000 1 1 1 1 F=A+CIN F=A S1 S2 S3 F1 F2 M CIN A0 S0 F0 B0 74x181 F3 COUT A1 B1 A2 B2 A3 B3 A=B P G

20 Chapter Summary Documentation Standards: - Gate symbols, Signals Active Levels, Bubble to Bubble Logic - Block diagram, Schematic Diagram, Timing Diagram. Combinational Logic design Structures: 1-Decoders : Binary Decoders, Cascading decoders 2-Encoders : Binary Encoder, Priority Encoder, Cascading Encoders, Encoder applications.

21 Chapter Summary 3- Multiplexers : MUX operation, Single/Multiple outputs MUX, Expanding MUXs 4- Demultiplexers : MUX/DMUX operation, Using Decoders as Demultiplexers. 5- XOR and XNOR Gates: Logic Symbols, Equivalent Symbols, Parity Circuits 6-Adders : Half Adder, Full Adder, Ripple Adder, Subtractor, Ripple Adder / Subtractor Unit, 7- Arithmetic/Logic Units of ALU

22 Next… Test 3 Reading Wakerly CH-7


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