1. Low Latency Clock Domain Transfer for Simultaneously Mesochronous, Plesiochronous and Heterochronous Interfaces Wade Williams Philip Madrid, Scott C. Johnson March 14, 2007

2. Low Latency Clock Domain Transfer 2 March 14, 2007 Presentation Overview Introduction Clock Domain Characteristics Design Constraints Solution System Response Time Additional Benefits Enhancements Questions

3. Low Latency Clock Domain Transfer 3 March 14, 2007 Introduction Increasing Levels of Integration  Mixed designs: System-On-A-Chip (SOC)  Independently clocked domains  Independently powered domains Faster External Interfaces  Interface clock frequencies are starting to exceed the internal logic clock rates  Clock frequencies exceeding 2 GHz

4. Low Latency Clock Domain Transfer 4 March 14, 2007 Clock Domain Characteristics Reference clock source mismatches (plesiochronous) PLL reference clock distribution PLL accumulated phase error Grid clock insertion delay Spread-Spectrum Temperature Voltage

5. Low Latency Clock Domain Transfer 5 March 14, 2007 D D Clock Domain (cont.) PLL D D D D D Clock A Clock B D

6. Low Latency Clock Domain Transfer 6 March 14, 2007 Design Constraints Minimized Latency, Maximized Throughput Unknown Phase Relationship Between Domains Controlled Frequency Mismatches (1% - 2%) Predictable Scheduling for Pipelining Manufacturability  Deterministic  Small design footprint  Simple design for quick productization

7. Low Latency Clock Domain Transfer 7 March 14, 2007 Solution This problem can be solved by building a system comprised of 3 major blocks  Circular FIFO –Performs the basic clock domain transfer  Pointer Tracking Logic –Maintains a consistent pointer separation and provides predictable latency across the interface  Digital Filter –Ensures system stability by filtering out errors due to sampling uncertainties

8. Low Latency Clock Domain Transfer 8 March 14, 2007 FIFO Basic clock domain transfer is achieved using a circular First-In First-Out (FIFO) queue. Example  8 entry FIFO  Write Pointer on Clock A (Frequency = 2)  Read Pointer on Clock B (Frequency = 3)  Clock B Frequency > Clock A Frequency

9. Low Latency Clock Domain Transfer 9 March 14, 2007 FIFO (cont.) 7 6 5 4 3 1 2 0 Clock A (Freq = 2) WrPtr Clock B (Freq = 3) RdPtr

10. Low Latency Clock Domain Transfer 10 March 14, 2007 FIFO (cont.) Slow Domain (Clock A) free-runs Fast Domain (Clock B) is gated to create the RdPtr Clock  Average frequency matches Clock A  Duty cycle and clock periods can vary Clock A (2) [WrPtr Clock] Clock B (3) RdPtr Clock

11. Low Latency Clock Domain Transfer 11 March 14, 2007 Pointer Tracking Logic This logic maintains a constant separation between the read and write pointers.  Operates exclusively in the faster clock domain  Leverages the fact that any changes in the pointer separation occur very slowly.

12. Low Latency Clock Domain Transfer 12 March 14, 2007 Pointer Tracking (cont.) 7 6 5 4 3 1 2 0 Clock A (Freq = 2) WrPtr[2:0] Clock B (Freq = 3) RdPtr[2:0] WrPtr[2] FF #0 FF #6 FF #7 Evaluate RdPtr Clock

13. Low Latency Clock Domain Transfer 13 March 14, 2007 Pointer Tracking (cont.) The synchronization chain runs at the FIFO data rate Information about the pointer location is preserved across the synchronization interface. Evaluate is a falling edge pulse generated by the MSB of the WrPtr[2:0]. It represents the WrPtr going to 0. When Evaluate pulses, we compare the RdPtr against the desired location.

14. Low Latency Clock Domain Transfer 14 March 14, 2007 Digital Filter This averages out the sample data and prevents false pointer corrections Sampling errors are introduce by:  Variations in the clock period of the RdPtr Clock  Metastability on the first sampling flop  High speed clock phase variations due to oscillations on the power supplies

15. Low Latency Clock Domain Transfer 15 March 14, 2007 Digital Filter (cont.) Variations in the RdPtr Clock period and duty cycle are intrinsic to this solution. Irregularities created by throttling the faster clock necessitate the use of a digital filter The effects of the clock period and duty cycle variations can be exacerbated by the sample rate of the final design.

16. Low Latency Clock Domain Transfer 16 March 14, 2007 Digital Filter (cont.) The sample rate and the RdPtr Clock can create ratios which inadvertently bias the data. This can not be completely solved with the digital filter. Additional refinements:  Allow hysterersis in the system  Alter the sample rate Clock ARdPtr Clk (I) RdPtr Clk (II)

17. Low Latency Clock Domain Transfer 17 March 14, 2007 Digital Filter (cont.) Metastability occurs when the data fails to satisfy the setup and hold requirements for the first synchronizing flop. It is expected that there will be periods of time when the front of the synchronization flop chain is operating in a metastable region. The digital filter can help reduce some of the sampling errors (noise) due to metastability.

18. Low Latency Clock Domain Transfer 18 March 14, 2007 Digital Filter (cont.) This design is not intended to track high speed phase variations between the two clock domains. Frequency oscillations on the power supplies are a primary contributor to this phenomenon. The digital filter can help average out the spurious samples and provide more accurate tracking.

19. Low Latency Clock Domain Transfer 19 March 14, 2007 System Response Time Using the eight entry FIFO example and a digital filter requiring 3 samples, a correction is possible every 3x8=24 slow clocks. In practice, the system will incur a full FIFO iteration before evaluating the first sample. This reduces the corrections to 1 in 32 clocks, allowing it to track a 3.1% clock difference.

20. Low Latency Clock Domain Transfer 20 March 14, 2007 Additional Benefits This design carries several beneficial properties  The desired pointer separation can be programmable  Initial pointer placement can be conservative  The tracking logic can be disabled  FIFO data traffic is quickly supported

21. Low Latency Clock Domain Transfer 21 March 14, 2007 Enhancements There are a few enhancements which are immediately feasible with this design  The logic can be mirrored  Pointer correction events can be pipelined  The tracking logic can operate off slightly earlier versions of their respective clock domains  The digital filter can be customized to the application

22. Low Latency Clock Domain Transfer 22 March 14, 2007 Trademark Attribution AMD, the AMD Arrow logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. in the United States and/or other jurisdictions. Other names used in this presentation are for identification purposes only and may be trademarks of their respective owners. © 2006 Advanced Micro Devices, Inc. All rights reserved.