1. Advanced Process Integration
ECE 7366
Advanced Process Integration
The MOSFET Structure
Dr. Wanda Wosik
Text Book: B. El-Karek, “Silicon Devices and Process Integration”

2. FET Structures

3. FET Structures: Design and Operation

4. Physics of an Ideal MOS Structure
Assume uniform and light doping
Si work function
Gate= p+ poly-Si
fm Work function
cSi Electron affinity
n+ poly-Si
Work function difference – here fms=0; usually it is not!

5. Flat band conditions (here fm=fs)
Description of Semiconductor Surface Conditions: Flat Band and Accumulation
Surface potential due to fms≠0
Qs=-Qm
Flat band conditions (here fm=fs)
No penetration of E-field to metal due to high conductivity
Note: fs indicates surface Fermi potential - type of conductivity and concentrations of carriers
Accumulation conditions (here fm=fs)

6. Description of Semiconductor Surface Conditions:
Voltage applied to the gate electrode
Depletion and Intrinsic Condition
Weak Intrinsic and onset of strong inversion

7. Operation of NMOS-FET Linear Region, Low VD
Saturation Region, Channel Starts to Pinch-Off
Saturation Region,
channel shortens beyond pinch-off, L’<L

8. Current-Voltage Characteristics: Saturation Mode
Pinch- off at VD=VG-VT
Long channel NMOS
Threshold voltage at the drain side

9. Inversion Carrier Distribution Important in Channel Region (@ Scaling)
Sub-bands QM
Inversion Carrier Distribution
Important in Channel Region Scaling)
surface
Classical
Predicted classical and quantum-mechanical inversion
Carrier distribution Average inversion depth as a function of effective surface field for 3 channel dopant levels
Total tox changes
Boltzmann approximation of F-D distribution
This & poly-Si depletion lead to a tox increase Capacitance Equivalent Thickness, CETs
Schrodinger and Poisson eqs.
Dx≈1.2 nm
Reduction of the inversion layer charge density
Broadening of the inversion layer
Decrease of the Cox due to the shift of Qinv away from the surface
Mobility decreases
Vth increases (bandgap widens due to high fields)

10. Non-Ideal MOS Structure
Workfunction in Si (in eV)
Fms for Al gates on p&n Si with varying dopants’ concentrations

11. Non-Ideal MOS Structure
Work function difference vs doping for Al gets and degenerate poly-silicon p+ and n+ type.
Note the symmetry of fms for poly-Si and asymmetry for Al gates
Band bending due to work function differences.
No charge in the oxide assumed

12. Dielectric Field in the oxide
MOS Capacitance
Dielectric Field in the oxide
Dual dielectric (nitride/oxide, high K/oxide etc.)
At the interface of dielectrics we have continuity of the displacement vector so:
Voltage on the gate
Equivalent Oxide Thickness
Qs total surface charge
Accumulation: majority carriers - fast response
Depletion: Ionized dopants – no minority carriers - fast response
Onset of Strong Inversion: minority carriers – slow i.e. response time limited by e-h generation
Since C=f(V) it is nonlinear so use differential capacitance:

13. MOS Capacitance at Low Frequencies
@vs=0 and us=ub
Flatband capacitance:
strong inversion
accumulation
depletion
weak inversion
Where Le is extrinsic Debye length (~ depth where carriers follow the voltage signal)
For p-type
For n-type
p-type
strong accumulation
Accumulation (surface concentration ns≈pp, Le C)
Cmax≈Cox
decreases for poly-Si gates!
accumulation
strong inversion
depletion
Depletion (surface concentration ns<<pp)
weak inversion
ys=-2fb
Inversion (surface concentration ns≈pp)

14. MOS Capacitance at Low & High Frequencies Parameter: Oxide ThicknessLF HF

15. Work-Function Difference in a Non-Ideal MOS Structure
Shift=f(fms)

16. Measurement of MOS Capacitance
Carrier generation within the depletion layer
xd established by DC gate voltage
strong accumulation
LF: 10Hz – 1kHz (depends on lifetime)
strong inversion f
HF: 100kHz – 1MHz (depends on lifetime)
Low frequency CV measured by quasi-static voltage technique: apply voltage ramp ~50mV/s and measure displacement current (electrometer). AC signal: dV≈±10-15mVG
For linear voltage ramp a= DVG/Dt capacitance:

17. Interface Traps Charge (donors or acceptors)
Amorphous/crystalline – interface is flat. (TEM)
Roughness  with  growth rate and  T.
Increasing surface roughness increases charges
Dangling bonds on Si surface  1015cm-2 (111)>>(100) (~3x)
After oxidation 1012 cm-2
Post Metallization Annealing (PMA)

18. Extraction of Interface-State Distribution
reminder
High-Frequency Capacitance Method =Terman method
HF signal high enough so interface traps do not recharge so Cit=0
F-level shift changes charge state of traps Qeff changes
@ the same surface potential
May increase with the sweeping voltage (high K dielectrics)

19. MOSFET Structure * * * CMP begins with STI
Dielectric here - everywhere* *
Poly-Si
CMP begins with STI
Leff can be smaller or larger than Lmet

20. NMOS Design & Fabrication
@ various energies
NMOS
Design & Fabrication
Implant LDD through poly gate
reduce E-field & suppress short channel effects
Deposit oxide and etch directionally spacers implant high concentrations  form silicides
silicides
Go to slide #26

21. Gated Diode + - Assume flat band condition @ VG=0V
Behaves as ½ of MOSFET with special emphasis on the gated junction
Depletion
No the junction – Fermi levels constant
the junction depletion layer larger and barrier smaller * *
Electrons in inversion layer come from n+ rather than from thermal generation + -
Reverse the junction electrons injected to n+ region and increase reverse current
Reverse biased junction
Vj - reverse
VT increases over VT|Vj=0 (or decreases for + Vj voltage)

22. Revere Biased Junction (1V) + Depleting Gate Voltage
Gated Diode
Revere Biased Junction (1V) + Depleting Gate Voltage
If surface R/G states present:
Surface generation velocity 
Saturation current
VT~ Vj=1V
Accumulating
Gate Voltage
For fully depleted surface ps&ns≈0 so
Interface generation current

23. Reverse Biased Junction: Accumulating Gate Voltage
At low voltage VG<0 large E because of 4 possible mechanisms:
Thermal generation
Defect Induced Leakage – quite high dopant concentrations
Impact Ionization and Junction Breakdown
Ban-to-Band Tunneling
Defect Induced Leakage
VG<0
Larger negative voltage VG shifts the depletion to higher doped region of n+ to the defect ★
Accumulation under the gate
Depletion at the junction

24. Reverse Biased Junction: Accumulating Gate Voltage
At low voltage VG<0 large E because of 4 possible mechanisms:
Thermal generation
Defect Induced Leakage – quite high dopant concentrations
Impact Ionization and Junction Breakdown
Ban-to-Band Tunneling
Corner and planar fields
Field in silicon tSi is large  it will  with |Vj|
Continuity of the displacement SiO2/silicon
Curvature VBR + -
Reverse biased junction  depletion layer around

25. Reverse Biased Junction: Accumulating Gate Voltage
Impact Ionization and Junction Breakdown
For + VG the field at the surface decreases to the bulk junction value – breakdown voltage increases.
Example for xj=300 nm, tox=10 nm and concentrations donors 5x1017cm-3 and acceptors 1017cm-3.
Avalanche multiplication within high field region tSi~65nm
Give the breakdown voltage:
BV≈ |Eox|tox+|ESi|tSi≈6.3V

26. Band-to-Band Tunneling
At low voltage VG<0 large E because of 4 possible mechanisms:
Thermal generation
Defect Induced Leakage – quite high dopant concentrations
Impact Ionization and Junction Breakdown
Band-to-Band Tunneling
It happens in gate overlapped highly doped n+ (NMOS) and p+ (PMOS) regions – large band bending and small depletion thickness
A=f(EG, mn*…)
Esi at the Si/SiO2 interface
ESi=f(VJG, ND)
For: VFB=0 

27. MOSFET Structure and Characteristics
Long and Wide Channel Device
Ys≈2fb Inversion layer formed in the channel
Leff can be smaller or larger than Lmet
Poly-Si
Important in I-V characteristics

28. Current-Voltage Characteristics: Linear Mode
Small voltage VD
Reasons for nonlinearity in the “linear regime”
mobility degradation
reduction of drain site: gate overdrive decreases with VD and VTdrain>VTsource
Gate S VG-VT VG-(VT+VD)
More accurate is Graduate Channel Approximation

29. Graduate Channel Approximation
Current-Voltage Characteristics: Linear Mode
Obtained using :
It accounts for for higher VT near the drain. Gives more accurate results

30. Current-Voltage Characteristics: Saturation Mode
Pinch- off at VD=VG-VT
Long channel NMOS
Threshold voltage at the drain side

31. Field and Charge Distribution at and above the Pinch-Off
Non-uniformity of voltage and E-fields (oxide & Si) distributions within the channel
Corresponding non-uniform distributions of charges within the channel
Channel treated as a resistor of effective length L’=L=dL with varying length and charge Qn(y) which drift with velocity nn(y) D)
Drain current P

32. Workfunction Difference
Samples prepared with different thickness but the same effective oxide charges
Fermi Level Pinning at high interface-state density sites at:
the oxide gate interface
Si-oxide interface
That results in weak dependence on of C-V fm
Slope: -Qeff/eox

33. Carrier Transport Through the Dielectric: Tunneling
High field ~ 1x107V/cm causes tunneling either by Fowler-Nordheim (F-N) or direct (dominates in thin oxides).
fox barrier height for: electrons 3.2 eV
Holes 4.6 eV

34. Carrier Transport Through the Dielectric: Tunneling
Leakage currents: leads to circuit instability power dissipation

35. Avalanche Injection to the Gate
From the Substrate
p-type silicon
MOS capacitor in deep depletion:
Surface potential high
Uniform doping
Non-uniform doping
Voltage across oxide small
Vox=VG-ys
ac-sinusoidal signal of high frequency and high amplitude
Avalanche Injection

36. Channel Conductance, gd
See next slide
Measured in [S]
In the linear mode the conductance [S]
In the saturation mode the conductance [S] gDsat should be “0”
Channel Transconductance, gm
Measured in [S]
In the linear mode [S/cm]
In the saturation mode [S/cm]

37. Body-Bias Effect on Threshold Voltage
VB changes depletion layer thickness
Either biased on purpose or develops during operation in circuits (see DRAM later)
Applied body-bias changes the threshold voltage
The sensitivity of VT to VB  with substrate doping

38. Body-Bias Effect on Threshold Voltage
Body effect: Source-Body can be also slightly forward
DRAM “write”: here both B & high potential (S & Capacitor charged) VT the source and channel S. When VS=VD-VT the node voltage:
DRAM
This max Vnode is supported by VG, can be reduced by decreasing body bias effect . Gate V required to support this Vnode max
Local adjustment of VT by VB

39. Substrate Current Body Effect affects Drain Current
Cheng and Hu 1999

40. Subthreshold Characteristics
Qn≈0; charge and ID drops for VG≤VT but not abruptly
ID is finite.
Subthreshold (injection to the channel as in BJT)
@ Source (surface)
@ Drain
Diffusion electron current in the channel
With interface states
ideality factor n=1-1.3
Off-current has to be small (ex. DRAMS etc.)
Weak inversion
Diffusion here
Drift here

41. Other Parameters of MOSFETs
Intrinsic Carrier Mobility
Intrinsic and Extrinsic Resistances
See current lines crowding
Eeff over inversion
Ohmic voltage drop on resistance. Very important in small devices!
Inversion layer thin: carriers confined (10 nm)  more scattering (many scattering mechanisms)
smaller mobility at the surface ~2-3x smaller than in the bulk
no dependence on oxide thickness
dependence on E-field
dependence on temperature
Applied voltage

42. Transit Time and Cutoff Frequency
Transit time of carriers in the channel in long devices (Ey<5x103 V/cm  vd=meffEy)
The gain of MOSFET
Gain=1
Cut off frequency in linear mode i.e. carriers follow the signal
Cut off frequency in saturation mode
Maximum oscillation frequency:
Power-out/power-in=1
Increase fmax: fT, Rs  gate, CGD

43. Scaling MOSFETs to Small Dimensions
Scaling considerations include the whole fabrication cycle:
Front-End of the line (FEOL) –all steps including silicidation
Back-End of the line (BEOL) – contacts, wiring, pads
Packaging.
Three aspects: minimum feature size, maximum allowable vertical and horizontal E fields, and carrier lifetime.
Lpoly<LPR - Etching
Lmet<Lpoly – poly_Si oxidation and lateral extend S/D
Leff<Lmet