1. DSP Builder v5.1.0
October 2005

2. Prerequisites Understanding of DSP Builder Understanding of Simulink
Understanding of SOPC Builder and Avalon Interface Specification
Understanding of IP MegaCore Design Flow
Understanding of Quartus II

3. Agenda DSP Builder Overview New Features in DSP Builder v5.1.0
Enhancements
Known Issues
Conclusion

4. Overview

5. Single Simulink Representation
System Level Design Tool
Development
Implementation
Verification
System Level Simulation of Algorithm Model
MATLAB/Simulink
RTL Implementation
RTL Simulation
Leonardo Spectrum
Precision, Synplify
Quartus II, ModelSim
System Level Verification of Hardware Implementation
Hardware
Single Simulink Representation
Algorithm
Modeling
System-level
Verification
Synthesis, Place ‘n Route, RTL Simulation
System Algorithm Design and FPGA Design Integrated

6. DSP Builder Overview Place and Route Creates HDL Code
Creates Simulation Testbench
Place and Route
Download Design to DSP Development Kits
HDL Synthesis
Verify in Hardware
Creates SOPC Builder Ready Component

7. Version Compatibility
DSP Builder
MATLAB/
Simulink*
Notes
5.0.0
R13, R14,
R14SP1, R14SP2
Recommends Quartus II v5.0
5.0.1
5.1.0
R14,R14SP1, R14SP2, R14SP3
Recommends Quartus II v5.1
Note (*) MATLAB/Simulink R13: Matlab v6.5, Simulink v5.0
MATLAB/Simulink R14: Matlab v7.0, Simulink v6.0
MATLAB/Simulink R14SP1: Matlab v7.0.1, Simulink v6.1
MATLAB/Simulink R14SP2: Matlab v7.0.4, Simulink v6.2
MATLAB/Simulink R14SP3: Matlab v7.1, Simulink v6.3

8. New Features

9. DSP Builder v5.1 New Features
HDL Import
Enhanced SOPC Builder Integration
Support Multiple Versions of IP MegaCores
Bit Width Parameterization
Name Propagation

10. HDL Import

11. HDL Import Import VHDL, Verilog or Quartus II Project
Simulink Simulation Model is Automatically Generated
Allows Co-Simulation
Does Not Require 3rd Party Simulator
Allow Multiple Instantiations

12. HDL Import Interface
Supports Hierarchical Designs with Multiple Entities
Add Verilog/VHDL Files or Select Quartus II Project
Set Top-Level Entity (Verilog or VHDL only)
Compile
Generate Simulink Model

13. HDL Import Requirements
Single Clock Domain
Synchronous Design
Supports Generic Memory and Logic Functions
Logic Elements
Memory
DSP Blocks
Does Not Support Device Specific Functions
Examples - PLL, LVDS, WYSIWYG
Refer to DSP Builder Reference Manual for Complete List of Supported MegaFunctions

14. Design Flow using HDL Import

15. What About SubSystemBuilder?
Import HDL File
User Creates Own Simulation Model
Speed Up Simulation Using Own Simulink Model
Can Use SubSystemBuilder If Design Contains Unsupported LPMs/MegaFunctions

16. Comparison of HDL Co-Design Features
Design Effort
Simulation Speed
HDL Import
Low
Average
SubSystem Builder
High
Note(1)
Hardware in the Loop (HIL)
Medium
Fastest
Link for ModelSim
Fast
Note: (1) User creates their own Simulink simulation model. Simulation speed
depends on the type of simulation model.

17. Enhanced SOPC Builder Integration

18. SOPC Builder Integration
User Can Build Any Avalon SOPC Component
Dragging and Dropping Avalon Interfaces into DSP Builder Design
Validate by Simulating in Simulink
Export to SOPC Builder by Generating HDL and PTF from Signal Compiler

19. Enhanced SOPC Builder Integration
Interface Blocks
Avalon Slave
Avalon Master
Wrapped Blocks
Avalon Read FIFO
Avalon Write FIFO
Multiple Slaves and Masters
Advanced Avalon Bus Support

20. Interface Blocks Low-level Access to Avalon Signals
All Ports have “Pass-Through” Behaviour
Allows Multiple Slaves/Masters
Mechanism for setting PTF variables
Dialog to Configure Mode of Operation
Avalon Slave
Avalon Master

21. Avalon Master User Configurable to Allow Subset of Signals
Modes of Operation
Flow Control
Pipeline Transfers
Burst Transfers

22. Avalon Master Signals Signal Type Signals Fundamental
clk, waitrequest, address, read, readdata, write, writedata, byteenable
Pipeline
readdatavalid, flush
Burst
burstcount
Flow Control
endofpacket
Other
irq, irqnumber

23. Input
Avalon Master Example
Output

24. Avalon Slave User Configurable to Allow Subset of Signals
Modes of Operation
Flow Control
Pipeline Transfers
Burst Transfers

25. Avalon Slave Signals Signal Type Signals Fundamental
clk, address, read, readdata, write, writedata, byteenable
Wait-State
waitrequest
Pipeline
readdatavalid
Burst
burstcount, beginbursttransfer
Flow Control
readyfordata, dataavailable, endofpacket
Other
irq

26. Input
Avalon Slave Example
Output

27. Wrapped Blocks Higher Level of Abstraction
Map Avalon Signals to a “Standard” Subset
Both Read/Write FIFOs Handle Streaming Data
Test Avalon Interface in Simulink Environment
Avalon Write FIFO
Avalon Read FIFO

28. Avalon Write FIFO Hierarchical Component Configuration Dialog
Data Type
Data Width
FIFO Depth

29. Avalon Write FIFO Internals
Look Under Mask
User Can Customize Functionality using Mask Editor

30. Avalon Write FIFO Signals
Description
TestData
Pass through simulation data to DataOut one cycle after Ready is asserted
Stall
Simulate stall conditions, and may cause underflow to SOPC component. When asserted, data provided by TestData is cached and no Avalon writes take place.
Ready
When asserted, indicates downstream hardware is ready for data.
DataOut
Output from FIFO
DataValid
Asserted when valid output is presented on DataOut

31. Avalon Read FIFO Hierarchical Component Configuration Dialog Data Type
Data Width
FIFO Depth

32. Avalon Read FIFO Internals
Look Under Mask
User Can Customize Functionality using Mask Editor

33. Avalon Read FIFO Signals
Description
Stall
Simulate stall conditions, applying backpressure to the SOPC Component. When asserted, data provided on Data fills up FIFO but no Avalon reads take place.
Data
Outgoing data from user’s design
DataValid
Asserted when valid signal is presented on Data
TestDataOut
Output from FIFO over Avalon Interface
TestDataValid
Asserted when valid output is presented on TestDataOut
Ready
When asserted, indicates slave is ready to receive data.

34. Testing Blocks Streaming Avalon Converter Not Synthesizable
Provides Data to Avalon Write FIFO
Collects Data from Avalon Read FIFO
Not Synthesizable

35. Avalon Write/Read FIFO Example

36. Simulink Simulation Avalon Blocks Accept Simulink Data
Use Standard Simulink Source/Sink Blocks
Sources: Constants, Sine Wave, MATLAB vars
Sinks: Display, Scope, File

37. HDL and PTF Generation Set Option to Generate PTF in Signal Compiler
VHDL Entity/Port Names Derived From Block
PTF File Automatically Generated
Needed for Import in SOPC Builder
Component Appears in SOPC Suite

38. SOPC Builder System Editor
Nios II
H/W
Core
+ DMAs
A view of most of the system in SOPC builder (missing off the screen is thing like the LEDs and buttons).
Note that Nios does not access the edge detector, only the DMAs. DMA_1 is used to write from memory to the edge detector. DMA_2 reads from the edge detector to memory.
LCD controller and camera write to memory – they have internal DMAs

39. What About Avalon Ports?
Only For Legacy Design
Allow One Slave Per Design
Avalon Slave Block Has Same Functionality
Except for Chip Select

40. Other New Features

41. IP MegaCore Support Access to Multiple Versions of IP
Versioned MegaCore
Blue Color
Recommended for New Designs
Legacy MegaCore
Gray Color
For Backwards Compatibility
Warnings Will Be Generated
Example:
Warning: The block ‘test/csc' is linked to 'MegaCoreAltr/csc', which is a legacy block in the library and should not be used in new designs.

42. Update IP MegaCore Automatic Update Manual Update Global Update
Create Two Variables in MATLAB
dspbuilder_reinstall_megacores = ‘on’
dspbuilder_auto_update_megacore=‘on’
Rerun setup_dspbuilder
Update MDL (Edit Menu) or Ctrl-D
Manual Update
Design Specific Update
update_megacores [design_name]

43. Design Parameterization Support
5.1
5.0
User can explore design optimization possibilities

44. Propagation of Signal Names

45. Enhancements

46. DSP Builder v5.1 Enhancements
Error Message Improvements
Simulation Performance Enhancements
Documentation Improvements

47. Improved Error Messaging
Hyperlinks in MATLAB command window
Pin-point Errors
Multiple errors displayed
Blocks causing error are highlighted

48. IP Simulation Simulation Time Speed Up Improved Memory Usage
Typically ~20% Faster
Improved Memory Usage
Previously Memory Grew Linearly During Simulation, Limiting Simulation Time
Less Variation in Simulation Time
Previously > 2x Difference in Run-Time Possible for Identical Simulations
Now Always Minimum
Simulation speed improvements
Reduced memory requirements

49. Documentation Improvements
Integration with Matlab Help system
Allows navigation and search in Matlab
Integrated with Matlab help

50. Known Issues

51. HIL and HDL Import Using SBF
Simulation Mismatch Using HIL or HDL Import Block with Signed Binary Fractional (SBF) Format
Convert SBF to Signed Using Binary Point Casting Blocks
SPR#189659

52. Unique Entity Names
Option to Generate Unique Hierarchical Names Cannot be Easily Unset
Option is Disabled by Default
To Enable:
dspbuilder_enable_unique_hierarchy_name = true;
SPR#189491

53. SignalCompiler Flow Shortcut
Shortcut for “Execute steps 1, 2 and 3” Fails for 3rd Party Synthesis Tools
Run Steps Separately
SPR#190351

54. Conclusion

55. Conclusion
DSP Builder Offers a Complete Integrated Platform with Seamless Flow From System Design to Hardware Design
HDL Import Allows HDL Co-Design
Enhanced SOPC Builder Integration
Simulation Speed Improvements
Improved Usability

56. Back-up Slides

57. References AN402: Black-Boxing in DSP Builder
AN403: Avalon Master/Slave Blocks in DSP Builder
DSP Builder Reference Manual
DSP Builder User Guide
DSP Builder Release Notes
DSP Builder Errata Sheet

58. DSP Builder Training Previous Training Material on DSP Builder Molson
AppsNet
DSP Technology Symposium

59. DSP Builder Roadmap 2005 2006 Q3 Q4 Q1 Q2 Q3 Q4 DSP Builder 5.1
HDL Import
Simulation Speed Improvements
Enhanced SOPC Builder Integration
DSP Builder 6.0
Multi-channel management blocks
External Memory Support
SOPC Datapath Integration
DSP Builder 6.1
Fixed-point data type
Frame-based simulation
HIL Improvements

60. Competitive Analysis Features DSP Builder v5.1.0 System Generator
RTL Import + 
Co-Processor Strategy
Hardware Co-Simulation
HDL Co-Simulation
Synthesis User Interface
System Generator has a more complete blockset. They cover more application spaces than DSP Builder. We should be much more competitive by 6.0, with the additional blocks that are planned.
+ = Pro
= Neutral
N/A = Not Available

61. Hardware in the Loop (HIL)
Simulation Acceleration
Instrumentation
Simple Hardware Interface
JTAG Connector
Source
Sink

62. HIL Design Flow Step 1 : HIL Block Configuration
Step 2 : Quartus II Compilation, SOF Program
Step 3 : Simulate
JTAG HDL
Wrapper
Configure
Compile/Program
Simulate

63. Co-simulate HDL using ModelSim
Bidirectional Link Between MATLAB/Simulink and ModelSim
Provided by Mathworks
System-Level Design
and Simulation
Co-simulation and
Verification
HDL Simulation
MATLAB
Simulink
Modelsim
Link to ModelSim

64. Link to ModelSim Design Flow
Step 1 : Insert HDL into Simulink as Black-Box
Step 2 : Configure VHDL Co-Simulation Block
Step 3 : Set Up ModelSim and Load Model
Step 4 : Start Simulation in Simulink
Configure
Set Up ModelSim
Simulate

65. Subsystem Builder Import HDL Design and Black-Box
Creates Simulink Symbol of Subsystem
User Creates Simulation Model

66. DSP Builder Path in MATLAB
Install Path Not Removed During Un-installation of DSP Builder v5.0
Conflict Due to Multiple Paths to Library
Edit startup.m MATLAB Script to Comment Out Path
<MATLAB install dir>\toolbox\local\startup.m
%path(path,'C:\altera\DSPBuilder\AltLib');