1. Hardware Design Environment Instructors: Fu-Chiung Cheng ( 鄭福炯 ) Associate Professor Computer Science & Engineering Tatung University

2. Outline Hardware Design Environment System Design Process Hardware Simulation Synthesis Process

3. Hardware Design Environment As the size and complexity of digital systems more computer-aided design (CAD) tool are introduced into the hardware design processed. The widespread use of Hardware description languages (HDL) is no more than a decade old. More and more tools and technologies for digital system design are coming…

4. Digital System Design Process Figure 1.1 (page 2) Design Idea ==> Behavioral Design ==> Pseudo Code.. ==> Data Path Design ==> Bus & Register Structure ==> Logic Design ==> Gate Wirelist, Netlist ==> Physical Design ==> Transistor List, Layout,... ==> Manufacturing ==> Chip or Board

5. Digital System Design Process Top-down design process Starting with a design idea Generating a chip or board

6. Data path Design Phase

7. Full Adder (Gate network)

8. `timescale 1 ns / 1 ns // A 6-gate full adder; this is a comment module fulladder (s, co, a, c, c); // Port declarations output s, co; input a, b, c; // Intermediate wires wire w1, w2, w3, w4; // Netlist description xor #(16, 12) g1 (w1, a, b); xor #(16, 12) g5 (s, w1, c); and #(12, 10) g2 (w2, c, b); and #(12, 10) g3 (w3, c, a); and #(12, 10) g4 (w4, b, a); or #(12, 10) g6 (co, w2, w3, w4); endmodule Full Adder (Verilog)

9. Hardware simulation

10. Verify Each Stage

11. Hardware Simulation

12. Verify each Design Stage

13. Simulating an XOR

14. Oblivious simulation.

15. Event driven simulation.

16. Categories of synthesis tools

17. Synthesis process.

18. Resource sharing.

19. Testing Digital System Design Issues: – Simulation – Synthesis – Test and Testability Test and Testability: – Test generation – Fault simulation – Test bench programs

20. Levels of abstraction Three common models Behavior Dataflow Structural

21. Behavioral Description Most abstract Describe functions in procedural form Good for – fast simulation of complex hardware units, – verification and functional simulation of design idea – modeling standard components and documentation Detail of hardware is unknown

22. Dataflow Description Concurrent representation of the flow and movement of data Not good for end-user or non-technical document Good for designer for describe components to be synthesized Examples: Self-timed library

23. Structural Description Lowest and most detailed level of hardware description Good for hardware synthesis Contain a list of concurrently active components and their interconnection Gate-level description Timing simulation (OK)