1. 1 Review Of “A 125 MHz Burst-Mode Flexible Read While Write 256Mbit 2b/c 1.8V NOR Flash Memory” Adopted From: “ISSCC 2005 / SESSION 2 / NON-VOLATILE MEMORY / 2.5 by: C. Villa et al” Class presentation of Advanced VLSI course by by Ashkan Jalili Ashkan Jalili Instructor: Dr. Fakhraie

2. 2 outline  Floating Gates  Conventional sense amplifiers  Proposed sense amplifier  Programming scheme  Chip specifications  Summary

3. 3 FLOATING GATE  Based on charges stored on FG and changing V th  Desired values: value = 1 : no charges on FG value = 1 : no charges on FG value = 0 : specific charge on FG value = 0 : specific charge on FG  Applying a specific gate voltage: I > 0 : cell value = 1 I > 0 : cell value = 1 I = 0 : cell value = 0 I = 0 : cell value = 0 Source N+ Floating Gate Tunnel Oxide Drain N+ Substrate P-type Control Gate

4. 4 MULTILEVEL CHARGING  Different levels of charging on the FG  Considering the amount of cell current rather than just sensing it’s presence or absence  Different V th for a 2bit/cell resulting in 4 levels of current showing 4 states i.e 2bits: I cell < I ref3 ➱ 2bits value = 00 I cell < I ref3 ➱ 2bits value = 00 I cell < I ref2 ➱ 2bits value = 01 I cell < I ref2 ➱ 2bits value = 01 I cell < I ref1 ➱ 2bits value = 10 I cell < I ref1 ➱ 2bits value = 10 I cell > I ref1 ➱ 2bits value = 11 I cell > I ref1 ➱ 2bits value = 11

5. 5 Conventional Sense Amplifiers Structure of a conventional sense amplifier[3] Structure of a conventional sense amplifier[3]

6. 6 Disadvantage of Conventional amplifiers  A constant high voltage is applied to all cells (higher than the largest V th ) resulting in wide range of current:  The circuit should have the ability to work in wide range of current from a few uA to several tens of uA  The current in cells with lower V th is large:  Large current increases the effect of parasitic resistance  Lager current increases power dissipation

7. 7 Sense amplifier scheme Proposed sense amplifier scheme[1] Proposed sense amplifier scheme[1] + - + - Precharger - I/V converter Comparator Latches Reference sense out Bit line Word line Iref Vref R0  Iref < 10µA  SA switched off as Icell > Iref MSB LSB

8. 8 Read scheme of proposed structure Structure of reading concept[1] Structure of reading concept[1] Out SA Ramp gen Reference Wordline Array Wordline Ref sense out Iref Ref 1 Ref 2 Ref 3 Decode Latch

9. 9 Design solution: voltage ramp read Read ramp, reference and array sense output[1] Read ramp, reference and array sense output[1] WL reset by ref3 trigger time Vgate 01001011 Vtref1Vtref2Vtref3 Reference triggers 000001011111 Array cell trigger Sense output 01 array cell Word line ramp Iref Icell SA trigger

10. 10 Conventional programming Scheme Conventional programming: Applied constant V g [4]  Constant V g is applied to all cell gates  Amount of desired charge is tuned by the pulse width  Disadvantage:  The threshold voltage distribution of programmed cells can be several volts (not suitable for low voltage operations)

11. 11 Programming scheme A sample threshold voltage distribution diagram [2] A sample threshold voltage distribution diagram [2]

12. 12 Improved programming scheme Introduced in 1995 a) Trapezoidal, b) and staircase, programming pulses [4] a) Trapezoidal, b) and staircase, programming pulses [4]  Easier to control V th distribution width  Higher programming speed can be obtained  Easier to generate on chip  V th will increase with every step  Changes depend on the amount of step

13. 13 Programming scheme Threshold voltage changes for different voltage steps [2]

14. 14 Programming scheme  Staircase voltage is applied to achieve narrow distribution width  The gate voltage in programming phase is varied from 1V to 9v with a step size of 75mV  3 phase is used for programming: 1.Content of memory is read and compared to the content of write buffer 2.Programs “10” and “01” cells executing a program/verify loop 3.Programs “00” cells applying a voltage ramp starting from the last used voltage level in phase 2, no verify is done

15. 15 16Mbit Bank Input Output Charge Pumps Ctrl logic 256 Mbit flash - Die photo [1]  16 banks of 64Mb  16 sectors / bank  64Kw / sector  Independent 64+3 sense amplifiers per bank  Die size 55mm 2 in 130nm Sense amps Ctrl logic Die photo [1] Die photo [1]

16. 16 Access time measurement [1] 65 ns Address input Data output Ref 3 sense out Word line ramp 10 ns/div Fastest slope conf (~250mV / ns) Access time measurement [1]

17. 17 Key feature table [1] Specifications of the chip [1]

18. 18 Summary  A new structure for sense amplifiers was proposed in order to remove the undesired effects of high currents due to high constant voltage applied to transistors in conventional sense amplifiers

19. 19 References 1.C. Villa et al., “A 125 MHz Burst-mode Flexible Read-While-Write 256 Mbit 2b/c 1.8V NOR flash memory,” ISSCC 2005 2.Tae-Sung Jung et al., “A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications,” JSSCC 1996 3.G. Campardo et al., “40-mm2 3V Only 50-MHz 64-Mb 2b/c NOR Flash Memory’” JSSCC 2000 4.G.J. Hemink et al., “Fast Accurate Programming Method for Multi- Level NAND EEPROMs,” Symposium on VLSI Technology Digest of Technical papers 1995

20. Thank you Any question?