1. TIM Phase A 1 SSL, 8/15/2007 Electric Field and Waves Instrument (EFW) Technical Interchange Meeting EFW Digital Electronics Digital Control Board (DCB) Michael Ludlam University of California - Berkeley

2. TIM Phase A 2 SSL, 8/15/2007 Overview Introduction Block Diagram Processor Control Logic Memory SLBM Timeline & Schedule Overview

3. TIM Phase A 3 SSL, 8/15/2007 Introduction The Data Controller Board interfaces with the S/C Bus, receiving TC and sending out TM (Science and HK). It provides the digital interface to the other boards, passing on TC and collecting HK and TM data. Science data is packetized and stored in memory before being telemetered out to the S/C. FPGA control logic is used for repetitive tasks. FSW is used for more complex operations.

4. TIM Phase A 4 SSL, 8/15/2007 Block Diagram

5. TIM Phase A 5 SSL, 8/15/2007 Z80 Processor Core Z80 8 bit processor will be incorporated into Actel FPGA (RTAX1000S). Core from CAST Inc uses approx. 40% of the RT part. Core is delivered with simulation test benches to support ModelSim analysis and place and route script (implements correct placement in part). Core also comes with example Z80 programs to test part and full documentation. EFW team is expecting to buy this core for breadboarding in Q3/Q4 2007.

6. TIM Phase A 6 SSL, 8/15/2007 Control Logic Remainder of Actel available to accommodate interface logic to control: S/C interface – TC & TM IDPU Board interfaces – HK, TC and TM. DPC board memory (Prom, EEProm, SRAM, SDRAM, Flash) Housekeeping Themis equivalent logic was contained in RT54SX72 part for 5 instruments. Selected part (RTAX1000S) contains more logic gates available after Z80 core implementation than an empty RT54SX part. EFW IDPU will require considerably less logic as it is only 1 instrument.

7. TIM Phase A 7 SSL, 8/15/2007 Memory It is expected that the same memory parts as Themis will be used: 8k Prom 128k EEProm 128k SRAM 256M SDRAM (Or nearest sized equivalent at time of purchase).

8. TIM Phase A 8 SSL, 8/15/2007 SLBM High and burst rate data to be stored to SLBM memory (Flash parts from 3D plus). 32 parts will make up the memory. Parts will be switched in banks of 4 parts providing isolation between separate banks and the rest of the DCB. Parts have been radiation tested by vendor (TID > 50kRad) but will need to be shielded to meet a 100kRad requirement. A technical note has be written (RBSP_EFW_TN06_SLBM) describing more details. Power consumption is expected to be approx. 0.5W SLBM has been sized to fit on 1 6U card with rest of DCB circuitry.

9. TIM Phase A 9 SSL, 8/15/2007 Timeline and Schedule Prototyping work is expected to start soon to allow ample time to implement Z80 core and prove correct functionality. Once the core is considered to be working well enough a breadboard will be manufactured containing most DCB (commercial equivalent) parts. A ETU board will follow this during Phase B.