1. Rachel Jiang, 2007 1 Interrupts All modern processors have some mechanism to allow peripherals/auxiliary circuitry to get the attention of the processor. there are usually several kinds of interrupts, with greater priority given to some interrupts than others. --Software processed by the CPU

2. Rachel Jiang, 2007 2 Interrupts Cont’d The CPU –controls all parts –is communicating with all other devices keyboard, mouse, Modem, printer,.... It is the responsibility of the CPU to process in time any request coming via one of the devices from the user for example: the user moved the mouse, now the position of the mouse-cursor needs to be updated on the screen. IO device –starts change; error; shutdown; internal error detection

3. Rachel Jiang, 2007 3 Interrupts On the 6809 Three tiers: – Each of the three tiers corresponds to an interrupt input pin. NMI (IV address: FFFD and FFFC) –Non Maskable Interrupt. This kind of interrupt is for the most important (or most impatient) interrupts. The 6809 gives highest priority to NMIs. FIRQ (IV: FFF6 and FFF7) –Fast Interrupt Request. This is a mid-level interrupt. An NMI will interrupt a FIRQ, but a FIRQ can interrupt an IRQ. Also, a FIRQ only pushes the PC and the CC before going to the FIRQ handler. IRQ (IV: FFF8 and FFF9) –This is the lowest level interrupt. It can be interrupted by both NMIs and FIRQs. Also, IRQ pushes all the registers on the stack before going to the IRQ handler.

4. Rachel Jiang, 2007 4 M6809

5. 5 M6809 registers

6. Rachel Jiang, 2007 6 Condition code register 8 different flag bits indicate processor status/control in the CC: C V Z N I H F E –C: indicates a carry / borrow was generated in the last operation. –V: the last operation resulted in a signed arithmetic overflow. –Z: indicates that the result of the last operation was a zero. –N: the result of the last operation was a negative (bit 7 is true). I: When is 1, interrupts requested on IRQ input will be ignored. The bit is set at system start-up and during interrupt processing. H: (1) a carry was generated by the lower four bits of the addition. F: When is 1, interrupts requested on FIRQ input will be ignored. The bit is set at system start-up and during interrupt processing. E: (1), indicates that all registers were pushed onto the stack prior to jumping to the interrupt handler. If 0, only the PC and CC were pushed. –This flag is used by the RTI instruction to restore the stack properly at the end of the interrupt handler.

7. Rachel Jiang, 2007 7 Reset vector –A reset signal (active low) will cause PC to be loaded with the address stored in FFFE FFFF –Used to start the execution of a program from an initial start condition Power down Power failure User press the reset key

8. Rachel Jiang, 2007 8 NMI An active low request on NMI pin will cause the INT. –All regs, are saved onto hardware stack –E bit is set –I and F flags are set to mask off any other interrupts –Nonmaskable (can not be disabled) –Higher prior than FIRQ, IRQ, and SWIs –ISR is terminated by RTI

9. Rachel Jiang, 2007 9 FIRQ A low level on the FIRQ input (active low), with the F bit clear, causes this interrupt to be served. –On accepting an FIRQ, the processor clears the E flag to save only PC and CC regs. Sets both the I and F bits to mask any further IRQ and FIRQ interrupts ISR is terminated by RTI

10. Rachel Jiang, 2007 10 IRQ If I bit is clear, a low level on the IRQ input pin (active low) causes this interrupt to occur at the end of the current instruction –Regs are pushed onto the hardware stack –Set E flag (indicate that it has saved the entire machine state –Set I bit to mask any further maskable interrupts –FIRQ may interrupt –ISR is terminated by RTI

11. Rachel Jiang, 2007 11 Summary NMI, IRQ: set E and I flags FIRQ: clear E flag NMI, FIRQ: set I and F bits NMI is triggered by an active low signal FIRQ is triggered by a low and F flag is clear IRQ is triggered by a low and I flag is clear

12. Rachel Jiang, 2007 12 exceptions An event that occurs during the execution of a program that disrupts the normal flow of instructions. –Traps Internally generated Occur when the program requests to do something An automatic procedure call (routines from OS) Terminate program that cause the trap –Interrupts Externally generated Occur when an external signal sends request Arrive asynchronously (from outside, at no specific time)

13. Rachel Jiang, 2007 13 Exceptions: Traps CPU interrupts CPU –Arrive synchronously –Occur due to something in instruction stream Overflow/underflow NaN (divide by zero) Illegal assembler instructions A trap handler (trap routine) is executed –OS take care the trap requests An automatic procedure call (trap handler) by the hardware

14. Rachel Jiang, 2007 14 Trap handler Is a routine, part of OS –After trap occurs, CPU transfer the control to a TH –Address locations –II: 60; OF:64; UF:68; DBZ:72; DiskError:76 What does trap handler do? –Print message –Terminate program that caused the trap.

15. Rachel Jiang, 2007 15 How to get addresses of TH? A fix section of mem. Holding the starting addresses of TH –This part of mem is called Branch Table –60 2000 II –64 3000OF –68 3600UF –72 5224DBZ –764180 DE –80 5364TTY (teletype) –886048Timer

16. Rachel Jiang, 2007 16 SWI Software interrupts –an instruction (OS call) that triggers an IRQ Can be used for debugging, tracing… –Non-maskable –Generated by SWI instruction –SWI2 and SWI3 operate in a similar way to the SWI but do not have as high a priority as the SWI –SWI IV: FFFA and FFFB –SWI2 : FFF4 and FFF5 –SWI3 :FFF2 and FFF3

17. Rachel Jiang, 2007 17 6 vectored interrupts when INT is acknowledged all regs are pushed onto Hardware stack (E=1) except for FIRQ, only pc and cc are pushed (E=0) NMI, SWI, FIRQ, IRQ, SWI2, SWI3 Low priority

18. Rachel Jiang, 2007 18 exercises 1. how many type of interrupts? –Describe the software/hardware interrupts 2. what is an interrupt vector? 3. which interrupt has the highest priority? 4. in which memory locations the IV for NMI is stored? How many types of traps –List the names and describe on what situation they occur

19. Rachel Jiang, 2007 19 CISC architecture The primary goal of CISC architecture is to complete a task in as few lines of assembly as possible. This is achieved by building processor hardware that is capable of understanding and executing a series of operations.

20. Rachel Jiang, 2007 20 The rise of CISC CISC Design: use microcode build rich instruction sets build high-level instruction sets

21. Rachel Jiang, 2007 21 What is CISC Complex Instruction Set Computer –designing chips that are easy to program and which make efficient use of memory. Each instruction in a CISC instruction set might perform a series of operations inside the processor. This reduces the number of instructions required to implement a given program, and allows the programmer to learn a small but flexible set of instructions. –Since the earliest machines were programmed in assembly language and memory was slow and expensive, the CISC philosophy made sense, and was commonly implemented in such large computers as the PDP-11 and the DECsystem 10 and 20 machines. Most common microprocessor designs --- including the Intel(R) 80x86 and Motorola 68K series --- also follow the CISC philosophy.

22. Rachel Jiang, 2007 22 advantages to a microcoded implementation the microcode memory can be much faster than main memory –an instruction set can be implemented in microcode without losing much speed over a purely hard-wired implementation. –a microprogrammed design can be modified to handle entirely new instruction sets quickly. –Using microcoded instruction sets, the IBM 360 series was able to offer the same programming model across a range of different hardware configurations.

23. Rachel Jiang, 2007 23 Build high-level instruction sets build programmer-friendly instruction sets to map directly from high-level languages. –simplify the compiler writer's task –allows compilers to emit fewer instructions per line of source code. Modern CISC microprocessors, such as the 68000, implement several such instructions –including routines for creating and removing stack frames with a single call.

24. Rachel Jiang, 2007 24 The disadvantages of CISC Earlier generations of a processor family generally were contained as a subset in every new version – instruction set & chip hardware become more complex with each generation of computers. –As many instructions as possible could be stored in memory with the least possible wasted space, slowing down the overall performance of the machine (different amounts of clock time to execute). –Many specialized instructions aren't used frequently enough to justify their existence --- approximately 20% of the available instructions are used in a typical program. –CISC instructions typically set the condition codes as a side effect of the instruction. Not only does setting the condition codes take time, but programmers have to remember to examine the condition code bits before a subsequent instruction changes them.

25. Rachel Jiang, 2007 25 RISC a type of microprocessor architecture – utilizes a small, highly-optimized set of instructions, rather than a more specialized set of instructions often found in other types of architectures. Characteristic of most RISC processors: one cycle execution time: –RISC processors have a CPI (clock per instruction) of one cycle. This is due to the optimization of each instruction on the CPU and a technique called ; pipelining: –a technique that allows for simultaneous execution of parts, or stages, of instructions to more efficiently process instructions; large number of registers: – the RISC design philosophy generally incorporates a larger number of registers to prevent in large amounts of interactions with memory –http://cse.stanford.edu/class/sophomore-college/projects- 00/risc/whatis/index.html

26. Rachel Jiang, 2007 26 Example CISC –MULT 2:3, 5:2 RISC –LOAD A, 2:3 LOAD B, 5:2 PROD A, B STORE 2:3, A

27. Rachel Jiang, 2007 27 CISC vs. RISC CICS: Emphasis on hardware –Includes multi-clock complex instructions –Memory-to-memory: "LOAD" and "STORE“ are incorporated in instructions –Small code sizes, high cycles per second, Transistors used for storing complex instructions RISC: Emphasis on software –Single-clock, reduced instruction only –Register to register: "LOAD" and "STORE“ are independent instructions, Low cycles per second, large code sizes, Spends more transistors on memory registers http://cse.stanford.edu/class/sophomore-college/projects- 00/risc/risccisc/

28. Rachel Jiang, 2007 28 How Pipelining Works http://cse.stanford.edu/class/sophomore- college/projects-00/risc/pipelining/index.html

29. Rachel Jiang, 2007 29 Exercises Assuming you are the designer of the next generation computer architect What type of architecture you would like to use? –RISC –CISC –?? –What would be the characteristics for a new architecture?

30. Rachel Jiang, 2007 30 Recent development The lines between the two architectures –have begun to blur – In fact, the two architectures almost seem to have adopted the strategies of the other. –CISC chips are now able to execute more than one instruction within a single clock. –allows CISC chips to make use of pipelining –it is now possible to fit many more transistors on a single chip. This gives RISC processors enough space to incorporate more complicated, CISC-like commands. RISC chips also make use of more complicated hardware, making use of extra function units for superscalar execution.