1. Design and Challenges of Passive UHF RFID Tag in 90nm CMOS Technology Student : Shu-Xian Liao Student Number : m98662007 Advisor :Chih-Ming Lin

2. References Yang Hong; Chi Fat Chan; Jianping Guo; Yuen Sum Ng; Weiwei Shi; Ho, Marco; Lai Kan Leung; Ka Nang Leung; Chiu Sing Choy; Kong Pang Pun; “Design and Challenges of Passive UHF RFID Tag in 90nm CMOS Technology”Electron Devices and Solid-State Circuits, 2008. EDSSC 2008. IEEE International Conference on ， 2008.Electron Devices and Solid-State Circuits, 2008. EDSSC 2008. IEEE International Conference on

3. I. INTRODUCTION II. RECTIFIER III. REGULATOR IV. CLOCK, ASK MODULATOR, DEMODULATOR, AND BASEBAND PROCESSOR V. CONCLUSION Outline

4. Introduction In this paper, a passive UHF RFID tag design is introduced. Due to the relatively large leakage current in 90nm CMOS technology, the MOS capacitor (cap) is replaced by a MOS cap with 2.5V IO characteristic, which occupies more area. The rectifier, regulator, demodulator, modulator, clock generator and baseband processor are all integrated into the tag IC

5. Introduction

6. Rectifier

8. Regulator

9. The reference voltage is 383mV at 27°C with 60ppm/°C tempco, while the tempco of bias current is 472ppm/°C as shown in Fig. 6.

10. Regulator

11. ASK Demodulator

12. Baseband processor

13. Conclusion A low-voltage, low-power, cost-effective, passive UHF RFID tag design using 90nm CMOS technology has been proposed in this paper. In the 90nm CMOS technology, due to the large leakage current, a MOS cap with 2.5V IO characteristic is chosen under the mutual compensation structure in voltage regulator design, to balance the tradeoffs between leakage current and area. All circuits have been designed in a 90nm CMOS technology to satisfy EPC C1G2 protocol, with emphasis on reduction of both power and chip area. Simulations have been done to verify the proposed ideas.

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