1. QUILT A GUI-based Integrated Circuit Floorplanning Environment for Computer Architecture Research and Education David H. Albonesi Computer Systems Laboratory Cornell University albonesi@csl.cornell.edu Gregory J. Briggs, Edwin J. Tan, Nicholas A. Nelson Electrical and Computer Engineering University of Rochester {grbriggs,etan,ninelson}@ece.rochester.edu This research was supported in part by National Science Foundation grant CCR-0304574.

2. Greg Briggs, University of Rochester Outline Q U I L T = Quick Utility for IC Layout and Temperature modeling Introduction Description of QUILT A few technical details QUILT in the classroom Future work Conclusions

3. Greg Briggs, University of Rochester Introduction An important part of our field is in making design tradeoffs Performance Cost Power Etc. How can students gain experience with these concepts?

4. Greg Briggs, University of Rochester Introduction How to gain experience? Fabricate some chips Time and money FPGA emulation Limited capacity Internal structure is not very accurate with respect to many of the tradeoffs we are facing today Interconnect delay Power Temperature Simulation Fast and reasonably accurate

5. Greg Briggs, University of Rochester Introduction Popular simulators (i.e. SimpleScalar [3] + Wattch [2] + HotSpot thermal modeler [12] ) Command line / text based input Tedious Prone to bugs DTB10.0003910000000000.0002750000000000.000060750000000-0.000663000000000 IntAlu20.0002467500000000.0004370000000000.000205000000000-0.001650000000000 ROB0.0003465000000000.0004690000000000.000451750000000-0.001223000000000 Dcache0.0007787500000000.000938000000000-0.000327000000000-0.000388000000000

6. Greg Briggs, University of Rochester Introduction QUILT Graphical interface Architectural-level floorplan Connects to HotSpot for thermal simulation (thermal performance directly limits power dissipation) Interconnect estimation More readily permits use of detailed simulators in the classroom

7. Greg Briggs, University of Rochester QUILT Interface

8. Greg Briggs, University of Rochester Floorplan Generation New FUs By Dimension Automatic Edit Modes Move Resize with constant area Resize (no constraint)

9. Greg Briggs, University of Rochester Mode Demo

10. Greg Briggs, University of Rochester Unit Info Transistor count SRAM size Chip area

11. Greg Briggs, University of Rochester Edit Menu

12. Greg Briggs, University of Rochester Interconnect Estimator Electrical interconnect Manhattan routing Optical interconnect predictions Point-to-point Computes delays relative to cycle time

13. Greg Briggs, University of Rochester Connects with HotSpot [12] Uses a “power trace file” for FU power dissipation inputs Simply runs the “sim- template” program included with HotSpot 2.0 [7]

14. Greg Briggs, University of Rochester HotSpot Demo

15. Greg Briggs, University of Rochester Graphics Production Useful for presentations, papers

16. Greg Briggs, University of Rochester Graphics Production The “zoom effect”

17. Greg Briggs, University of Rochester A Few Technical Details QUILT was written using Sun Java™ and its standard libraries. Java object model makes the code easier to extend, and avoids bugs Therefore, multi-platform Tested fully under Linux and Windows Packaged as a single JAR file which includes source code, yet you can run it just by double-clicking

18. Greg Briggs, University of Rochester Teaching and Research GUI is better than text interface Less error prone More intuitive More efficient and time saving Engineering students have been shown to be visually-oriented and hands-on learners [5]

19. Greg Briggs, University of Rochester An Exercise Using QUILT 1. Students modify floorplans to create new proposed designs  Area and interconnect delay estimates 2. Simulate via HotSpot / SimpleScalar or other simulator 3. View thermal results and produce graphics

20. Greg Briggs, University of Rochester Many Possible Exercises Tradeoffs between temperature, performance, interconnect delay Any exercise involving HotSpot becomes more feasible because of QUILT’s ease of use

21. Greg Briggs, University of Rochester Extensible / Future Work Java object model makes it easier to add new functionality Technology nodes More accurate or new interconnect models Floorplan macros Online help Etc. Open source: the community is invited to extend this tool www.ece.rochester.edu/research/acal/quilt/

22. Greg Briggs, University of Rochester Conclusions QUILT eases the study of interconnect delay and temperature (which limits power dissipation), two issues of importance for computer architects QUILT avoids the hassle, debugging, and errors involved in text-based simulator set-up Visualizations made by QUILT enhance learning

23. Greg Briggs, University of Rochester Questions? For more information and downloads, please visit: www.ece.rochester.edu/research/acal/quilt/ www.ece.rochester.edu/research/acal/quilt/ Thank You