1. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig 1 EECS 527 Paper Presentation High-Performance Global Routing with Fast Overflow Reduction - by Huang-Yu Chen, Chin-Hsiung Hsu, and Yao-Wen Chang Presented by Yaoyu Tao Department Electrical Engineering and Computer Science University of Michigan, Ann Arbor 10/2011

2. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig EECS 527 Paper Presentation  Outlines  Introduction  Problem Formulation  Routing Methodology Pre-routing Initial Iterative Monotonic Routing Iterative Forbidden-Region Rip-up/Rerouting (IFR) Layer Assignment  Experimental Results  Q & A 2

3. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Introduction State-of-the-art routing techniques  maze routing A*-search routing pattern routing monotonic routing multi-commodity flow integer linear programming (ILP)  Not clear on their capability to handle the upcoming design challenges 3

4. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Introduction  State-of-the-art Routers  Based on INR (iterative negotiation-based rip-up/rerouting)  INR becomes the main stream due to its great ability to spread out congestion as well as to reduce the overflow  Lagrange Relaxation (IR) mathematical basis to improve the INR 4

5. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Introduction  Developments on this paper  New global router - NTUgr, that contains 3 major steps: pre-routing, initial routing and enhanced INR  New techniques in pre-routing Congestion-hotspot historical cost pre-increment Small bounding-box area routing  Enhanced INR Multiple forbidden regions expansion Critical subnets rerouting selection Look-ahead historical cost increment 5

6. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Problem Formulation  Routing & Goal  Routing region - partitioned into global cells and a 2D or 3D routing graph composed of nodes (global tile nodes) and edges (global edges)  Each global edge is associated with a capacity  Objectives of global routing – Minimize the total overflow  Prioritized order of ISPD’08 Total overflow Maximum overflow Weighted total wire length 6

7. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Some basics  Global tile node & global edge  Overflow: the amount of routing demand that exceeds the given capacity 7 Global tile node Global edge Tile Tile boundary

8. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Some basics  State-of-the-art INR  Proposed in PathFinder [McMurchie and Ebeling, FPGA’95]  Spreads the congested wires iteratively  At the (i)-th iteration, the cost of a global edge e:  b e : base cost of using e,  p e : # of nets passing e,  h e (i) : historical cost on e,  INR may get stuck as the number of iterations increases

9. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Routing Methodology – Flow Chart  Flow of the global router  Three new techniques  2 nd place of ISPD 2008 Global Routing Contest 9 3D Benchmark 3D  2D capacity mapping Enhanced 2D routing 2D  3D layer assignment 3D routing result Prerouting Initial Routing Iterative Forbidden-region Rip-up/rerouting (IFR)

10. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Routing Methodology - Prerouting 10 3D Benchmark 3D  2D capacity mapping Enhanced 2D routing 2D  3D layer assignment 3D routing result PreroutingPrerouting Initial Routing Iterative Forbidden-region Rip-up/rerouting (IFR)

11. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Routing Methodology - Prerouting  Pre-routing  Congestion-hotspot Historical Cost Pre-increment Mainly for difficult routing instances, e.g., ISPD’07 newblue3 circuit Handle with high pin density Pre-increment the historical cost h e, in cost function (b e + h e ) ・ p e For ith global edges lying around the high-pin-density tiles before going into the INR procedures Achieve the least 31024 overflows for newblue3 ever in the literature  Small Bounding-box Area Routing  First route the subnets with smaller bounding-box areas since they have less flexibility 11

12. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Routing Methodology – Initial Iterative Monotonic Routing 12 3D Benchmark 3D  2D capacity mapping Enhanced 2D routing 2D  3D layer assignment 3D routing result Prerouting Initial Routing Iterative Forbidden-region Rip-up/rerouting (IFR)

13. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Routing Methodology – Initial Iterative Monotonic Routing  Initial Iterative Monotonic Routing  First stage that completes all subnets in the whole chip  Monotonic paths: this stage stops when the overflow reduction at the (i+1)-th iteration is less than 5% from the i-th iteration 13

14. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Routing Methodology - IFR 14 3D Benchmark 3D  2D capacity mapping Enhanced 2D routing 2D  3D layer assignment 3D routing result Prerouting Initial Routing Iterative Forbidden-region Rip-up/rerouting (IFR)

15. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Routing Methodology - IFR 15 

16. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Routing Methodology - IFR  Modified p e in IFR  P e is usually set as d e /c e  In proposed IFR  Multiple Forbidden-Regions Expansion  Identify the congested regions, called multiple forbidden regions expansion  Forbidden Region: Introducing overflows in this region is almost forbidden, or it would incur huge cost penalty  Three phases for multiple forbidden regions construction in IFR 16

17. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Routing Methodology - IFR 17 

18. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Routing Methodology - IFR  Multiple Forbidden-region Construction at the first phase 18

19. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Routing Methodology - IFR  Second Phase  Invoked when the number of overflows in the first phase stops decreasing and gets stuck at local optimal solution  New technique: Region Propagation Leveling (RPL)  “Inherit” all forbidden regions at the previous iterations and then expands these forbidden regions simultaneously  Avoids the local optima solutions in the first phase 19

20. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Routing Methodology - IFR  Effects of RPL 20

21. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Routing Methodology - IFR  Third Phase  Starts when the current number of overflows is less than 0.5% of the total overflows after the initial iterative monotonic routing  Final expansion – expand the forbidden region to the entire routing graph to quickly reduce the remaining overflows  Why? Because INR becomes less effective in reducing the overflows when the total overflows become smaller 21

22. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Routing Methodology - IFR  Comparisons of Congested Regions 22 BoxRouterNTHU-Route 1.0NTUgr (Ours) TerminologyBox Congested region Forbidden region ShapeRectangular Rectilinear # of regionsSingle boxSingle regionMultiple regions Objective Performing progressive ILP Selecting rerouting nets Performing different cost functions Simultaneou s expansion No Yes

23. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Routing Methodology – Critical Subnets Rerouting Selection  New speed-up scheme into IFR – Critical Subnets rerouting selection  Reduce the number of rerouting subnets in each iteration  Iterative rip-up/rerouting takes the most run-time, thus the key for speed-up is to reduce the number of rerouting subnets in each iteration  Only critical subnets are ripped-up and rerouted in IFR  Criterion for a critical subnet n, S is a constant and e is a global edge passed by n  In this paper, S is set to be -1 and obtain about 1.21x speedup 23

24. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Routing Methodology – Look-ahead Historical Cost Increment  Recall: main advantage of INR is the great ability to spread out congestion (overflows)  h e Update scheme for most state-of-the-art routers, where K is a constant, and c e and d e represent the capacity and demand of e  Conventional algorithm gets stuck in local optima solutions  Why? Because it performs less effective as the number of iterations increases and cannot minimize the overflows but just exchange the overflow regions instead 24

25. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Routing Methodology – Look-ahead Historical Cost Increment & Layer Assignment  New updating scheme  N > o represents a positive integer  Not only increase the historical cost on the global edges with overflows, but also on those near-overflow global edges  In this paper, N = K = 1, improves the quality of the router  Layer Assignment: 2-D to 3-D in non-decreasing order of their wire length  In this paper, layer assignment prefers the wire and via sharing 25

26. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Experimental Results  NTUgr in C++ on 2.8GHz AMD Opteron Linux workstation with 12 GB memory  Comparisons with state-of-the-art global routers in literature  ISPD’07 and ISPD’08  Proposed NTUgr obtains the best routing solutions for the most difficult instance, newblue3 (with only 31024 overflows) and newblue4 (with only 142 overflows)  High-quality results for the ISPD’07 and ISPD’08 benchmarks for both overflow and runtime 26

27. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Experimental Results  Achieved 1.94X speed up and better overflow reduction with similar total wire length 27

28. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Experimental Results  3-D ISPD’07 Results 28

29. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig Experimental Results  3-D ISPD’08 Results 29 The best solution in the literature!

30. VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig EECS 527 Paper Presentation Thanks! Q & A 30