Presentation is loading. Please wait.

Presentation is loading. Please wait.

CMOS Analog Design Using All-Region MOSFET Modeling 1 CMOS Analog Design Using All-region MOSFET Modeling Chapter 3 CMOS technology, components, and layout.

Published byIra Benson Modified over 9 years ago

Similar presentations

Presentation on theme: "CMOS Analog Design Using All-Region MOSFET Modeling 1 CMOS Analog Design Using All-region MOSFET Modeling Chapter 3 CMOS technology, components, and layout."— Presentation transcript:

1 CMOS Analog Design Using All-Region MOSFET Modeling 1 CMOS Analog Design Using All-region MOSFET Modeling Chapter 3 CMOS technology, components, and layout techniques

2 CMOS Analog Design Using All-Region MOSFET Modeling 2 Simplified CMOS process flow p-type substrate STI (b) STI Nitride Photoresist p-type substrate (a) Oxide Photo- resist Poly STI p-type substrate STI p-well n-well (d) Photo- resist Poly p-type substrate p-welln-well (c) STI n + poly p + poly n+n+ n+n+ p+p+ p+p+ p-type substrate p-well n-well STI (e) Oxide spacer n + poly p + poly n+n+ n+n+ p+p+ p+p+ p-type substrate STI p- well n-well STI (f) Oxide spacer p + poly n+n+ n+n+ p+p+ p+p+ p-type substrate STI p-well n- well STI (g) n + poly

3 CMOS Analog Design Using All-Region MOSFET Modeling 3 CMOS structure Triple-well process p-substrate deep n-well n-well p-well n+n+ n+n+ p+p+ p+p+ Transistors in deep- submicron process

4 CMOS Analog Design Using All-Region MOSFET Modeling 4 180 nm technology node nMOSpMOS Supply voltage1.3 - 1.5V Thin oxide3 nm L gate 130 nm150 nm VTVT 0.3 V (130 nm)-0.24 V (150 nm) I Dsat (1.5V) 0.94 mA/  m0.42 mA/  m I off 3 nA/  m g msat 860 mS/mm430 mS/mm C j (0V) 0.65 fF/  m 2 0.95 fF/  m 2 Silicide ( S, D and poly) 3 - 5  /sq Parameters of a six-metal-layer 180-nm CMOS technology node

5 CMOS Analog Design Using All-Region MOSFET Modeling 5 Integrated resistors h L W In the general case

6 CMOS Analog Design Using All-Region MOSFET Modeling 6 Resistivity of some metals Metal (bulk)Resistivity at 20 o CTCR Aluminum 2.8 · 10 -6  -cm 3800 ppm/ o C Copper 1.7 · 10 -6  -cm 4000 ppm/ o C Gold 2.4 · 10 -6  -cm 3700 ppm/ o C Sheet resistance of a copper layer of 1000 nm depth

7 CMOS Analog Design Using All-Region MOSFET Modeling 7 Polysilicon resistors CMOS Analog Design Using All-Region MOSFET Modeling 7

8 8 Summary of resistors in CMOS technology Resistor typeSheet resistance (  /sq) Temperature coefficient (ppm/ o C) Voltage coefficient (ppm/V) n + Polysilicon100-80050 p + Polysilicon200 50 n + / p + Polysilicon (silicided) 5 n + Diffusion501500500 p + Diffusion1001500500 n-Well1000250010000

9 CMOS Analog Design Using All-Region MOSFET Modeling 9 The MOS transistor as a resistor Example: Verify that, in strong inversion, the equivalent resistance between source and drain of an MOS transistor at V DS =0 is given by V Q is the dc potential at the source.

10 CMOS Analog Design Using All-Region MOSFET Modeling 10 Metal-insulator-metal capacitors (a) Substrate C1C1 C2C2 C3C3 C parasitic C=C 1 +C 2 +C 3 Metal 1 Metal 2 Metal 3 Metal 4 Top view Cross section (b) ( a) vertical parallel plate structure, (b) lateral flux capacitor.

11 CMOS Analog Design Using All-Region MOSFET Modeling 11 Metal-oxide semiconductor capacitors (a) Poly-semiconductor (b) poly-poly capacitors VCC is typically around 100 ppm/V TCC is of the order of 20 ppm/ o C.

12 CMOS Analog Design Using All-Region MOSFET Modeling 12 MOSFET gate capacitors - 1 Gate capacitors in a p-well CMOS technology

13 CMOS Analog Design Using All-Region MOSFET Modeling 13 MOSFET gate capacitors - 2 experiment theory

14 CMOS Analog Design Using All-Region MOSFET Modeling 14 Intrinsic capacitances of the MOS transistor for V DS =0 MOSFET gate capacitors - 3 In accumulation In strong inversion

15 CMOS Analog Design Using All-Region MOSFET Modeling 15 In accumulation In inversion, a similar expression holds MOSFET gate capacitors - 4

16 CMOS Analog Design Using All-Region MOSFET Modeling 16 Summary of capacitors in CMOS CMOS Analog Design Using All-Region MOSFET Modeling 16 Capacitor typeCapacitance per unit area ( aF/  m 2 ) Temperature coefficient (ppm/  C) Voltage coefficient (ppm/V) MOM1502010 MOM (combined lateral and vertical structure) 2002010 MOS gate (biased)500020010000 MOS (heavily doped Si option) 10002010 MIM (thin oxide option) 10002010 Poly-poly10002010

17 CMOS Analog Design Using All-Region MOSFET Modeling 17 Inductors Example: Inductance of a 5- turn spiral inductor with an average radius of 50  m. Planar spiral inductor

18 CMOS Analog Design Using All-Region MOSFET Modeling 18 Bipolar transistors (BJTs) in CMOS Flow of carriers in the CMOS-compatible bipolar junction transistor

19 CMOS Analog Design Using All-Region MOSFET Modeling 19 BJTs in triple-well CMOS

20 CMOS Analog Design Using All-Region MOSFET Modeling 20 Latchup Parasitic bipolar transistors in CMOS technology which may lead to latchup. (a) Cross section of the CMOS structure; (b) Equivalent circuit of the parasitic bipolar transistors and resistors

21 CMOS Analog Design Using All-Region MOSFET Modeling 21 Optical lithography - 1 Wafer Mask Photoresist Ultraviolet light

22 CMOS Analog Design Using All-Region MOSFET Modeling 22 SourceWavelength (nm) Intended resolution (nm) Year of introduction G-line *4361000 I-line *3655001984 KrF laser248 2501989 ArF laser1931002001 F 2 laser15765** *Filtered spectral components of high-pressure Hg or Hg-rare gas discharge lamps. ** The technology was abandoned. Optical lithography - 2 Wavelength used for optical lithography

23 CMOS Analog Design Using All-Region MOSFET Modeling 23 Optical lithography - 3 Optical proximity correction (OPC) counteracts lithography distortions

24 CMOS Analog Design Using All-Region MOSFET Modeling 24 MOSFET layout - 1 Mask layout and cross section of a CMOS inverter. N-well and P-well contacts not shown. Dashed lines represent metal connections

25 CMOS Analog Design Using All-Region MOSFET Modeling 25 Source/drain implant Shaded region Asymmetry MOSFET layout - 2 Diagonal shift in the source drain regions of a transistor due to a tilted implant

26 CMOS Analog Design Using All-Region MOSFET Modeling 26 NoNo Rule 1Same structure 2Same shape, same size 3Same orientation 4Same surroundings 5Minimum distance 6Common-centroid geometries 7Same temperature Rules for minimizing systematic mismatch of integrated devices MOSFET layout - 3

27 CMOS Analog Design Using All-Region MOSFET Modeling 27CMOS Analog Design Using All-Region MOSFET Modeling 27 Matching improvement by the addition of dummy devices for the layout of two resistors with a resistance ratio of 2/1: (a) unconnected dummy resistors (b) connected dummy resistors Unconnected dummy Conn. dummy MOSFET layout - 4

28 CMOS Analog Design Using All-Region MOSFET Modeling 28 (a) C ox C ox +  C ox C ox +2  C ox C ox +3  C ox A B A B A B B A (b) MOSFET layout - 5 Mock layouts of some possible common-centroid geometries for improved matching. Transistors with the same label are connected in parallel.

29 CMOS Analog Design Using All-Region MOSFET Modeling 29 A differential pair with a folded layout AB C DE AB C DE C DE AB MOSFET layout - 6

30 CMOS Analog Design Using All-Region MOSFET Modeling 30 AB C DE F G C D E A B F G B A G F C DE MOSFET layout - 7 A third device is added to the differential pair without degrading the symmetry of the layout

31 CMOS Analog Design Using All-Region MOSFET Modeling 31 Common-centroid layout of a differential pair. CMOS Analog Design Using All-Region MOSFET Modeling 31 A B D E C A C B E D C MOSFET layout - 8

32 CMOS Analog Design Using All-Region MOSFET Modeling 32 Current mirror with an attenuation factor of 16: (a) Schematic; (b) Mock layout. I in (b) I out I in (a) MOSFET layout - 9

Download ppt "CMOS Analog Design Using All-Region MOSFET Modeling 1 CMOS Analog Design Using All-region MOSFET Modeling Chapter 3 CMOS technology, components, and layout."

Similar presentations

BASIC BLOCKS : PASSIVE COMPONENTS 1. PASSIVE COMPONENTS: Capacitors  Junction Capacitors  Inversion Capacitors  Parallel Plate Capacitors Resistors.

BASIC BLOCKS : PASSIVE COMPONENTS 1. PASSIVE COMPONENTS: Capacitors  Junction Capacitors  Inversion Capacitors  Parallel Plate Capacitors Resistors.
Course: Analog Circuit Design Time schedule: Tu 11.00-13.00 We14.00-16.00 Th14.00-16.00 Office hours: Tu 16.00-18.00 Exams: Feb. (2), Jun.-Jul. (2), Sep.

Course: Analog Circuit Design Time schedule: Tu We Th Office hours: Tu Exams: Feb. (2), Jun.-Jul. (2), Sep.
CMOS Fabrication EMT 251.

CMOS Fabrication EMT 251.
MODULE SYSTEM LOGIC GATE CIRCUIT DQ CMOS Inverter ASIC Full-Custom Semi-Custom Programmable FPGA PLD Cell-Based Gate Arrays General Purpose DRAM & SRAM.

MODULE SYSTEM LOGIC GATE CIRCUIT DQ CMOS Inverter ASIC Full-Custom Semi-Custom Programmable FPGA PLD Cell-Based Gate Arrays General Purpose DRAM & SRAM.
Analog VLSI Design Nguyen Cao Qui.

Analog VLSI Design Nguyen Cao Qui.
VLSI Design Lecture 2: Basic Fabrication Steps and Layout

VLSI Design Lecture 2: Basic Fabrication Steps and Layout
1 ELEC 422 Applied Integrated Circuit Design Section 2: MOS Fundamentals Chuping Liu [Adapted from Rabaey’s Digital Integrated Circuits, ©2003, J. Rabaey.

1 ELEC 422 Applied Integrated Circuit Design Section 2: MOS Fundamentals Chuping Liu [Adapted from Rabaey’s Digital Integrated Circuits, ©2003, J. Rabaey.

A Primer on CMOS Technology. Objectives: 1.To Introduce about CMOS technology.

A Primer on CMOS Technology. Objectives: 1.To Introduce about CMOS technology.
Introduction to CMOS VLSI Design Lecture 3: CMOS Transistor Theory David Harris Harvey Mudd College Spring 2004.

Introduction to CMOS VLSI Design Lecture 3: CMOS Transistor Theory David Harris Harvey Mudd College Spring 2004.
Introduction to CMOS VLSI Design Lecture 5 CMOS Transistor Theory

Introduction to CMOS VLSI Design Lecture 5 CMOS Transistor Theory
Adapted from Digital Integrated Circuits, 2nd Ed. 1 IC Layout.

Adapted from Digital Integrated Circuits, 2nd Ed. 1 IC Layout.
VLSI Design CMOS Transistor Theory. EE 447 VLSI Design 3: CMOS Transistor Theory2 Outline Introduction MOS Capacitor nMOS I-V Characteristics pMOS I-V.

VLSI Design CMOS Transistor Theory. EE 447 VLSI Design 3: CMOS Transistor Theory2 Outline Introduction MOS Capacitor nMOS I-V Characteristics pMOS I-V.
Lecture 11: MOS Transistor

Lecture 11: MOS Transistor
Introduction to CMOS VLSI Design Lecture 0: Introduction

Introduction to CMOS VLSI Design Lecture 0: Introduction
Introduction to CMOS VLSI Design Lecture 3: CMOS Transistor Theory

Introduction to CMOS VLSI Design Lecture 3: CMOS Transistor Theory
The metal-oxide field-effect transistor (MOSFET)

The metal-oxide field-effect transistor (MOSFET)
For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN0-201- 44494-1. © 2002.

For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002.
Introduction to CMOS VLSI Design Lecture 3: CMOS Transistor Theory David Harris Harvey Mudd College Spring 2004 from CMOS VLSI Design A Circuits and Systems.

Introduction to CMOS VLSI Design Lecture 3: CMOS Transistor Theory David Harris Harvey Mudd College Spring 2004 from CMOS VLSI Design A Circuits and Systems.
11/3/2004EE 42 fall 2004 lecture 271 Lecture #27 MOS LAST TIME: NMOS Electrical Model – Describing the I-V Characteristics – Evaluating the effective resistance.

11/3/2004EE 42 fall 2004 lecture 271 Lecture #27 MOS LAST TIME: NMOS Electrical Model – Describing the I-V Characteristics – Evaluating the effective resistance.

Similar presentations

Ads by Google