1. ECFA ILC Workshop, November 2005, ViennaLadislav Andricek, MPI für Physik, HLL DEPFET Project Status - in Summary Technology development thinning technology steering chips Switcher II r/o chips Curo II tolerance against ion. radition beam test 55 Fe

2. ECFA ILC Workshop, November 2005, ViennaLadislav Andricek, MPI für Physik, HLL DEPFET Principle Drain Source Gate  fully depleted sensitive volume  internal amplification  no interconnection strays  charge collection in "Off" state, readout on demand J. Kemmer & G. Lutz, 1987

3. ECFA ILC Workshop, November 2005, ViennaLadislav Andricek, MPI für Physik, HLL DEPFET Principle  fully depleted sensitive volume  internal amplification  no interconnection strays  charge collection in "Off" state, readout on demand J. Kemmer & G. Lutz, 1987 g q (pA/e - ) measured value Simulation internal amplification effective channel length L (  m)

4. ECFA ILC Workshop, November 2005, ViennaLadislav Andricek, MPI für Physik, HLL Matrix operation Only selected rows dissipate power but Sensor still sensitive even with the DEPFET in OFF state T ROW ≈ 50ns Row wise read out and row wise CDS!

5. ECFA ILC Workshop, November 2005, ViennaLadislav Andricek, MPI für Physik, HLL Compact linear DEPFETs Double pixel cells: reduces the required read out speed by 2  doubles the number of read out channels smallest pixel cell 22.5 x 36 μm 2 limited by technology: smallest feature size ≈2μm Gates Common Sources Clears D1D2  double poly-silicon/double metal Technology

6. ECFA ILC Workshop, November 2005, ViennaLadislav Andricek, MPI für Physik, HLL Module Concept: "all-silicon module" Thinned sensor (50 µm) in active area Chips are thinned to 50 μm, connection via bump bonding Cavities in frame can save material Thick support frame (~300 µm) Material budget (1 st layer, incl. steering chips and frame) ≈ 0.11 %X 0

7. ECFA ILC Workshop, November 2005, ViennaLadislav Andricek, MPI für Physik, HLL Top Wafer Handle Wafer a) oxidation and back side implant of top wafer b) wafer bonding and grinding/polishing of top wafer c) process  passivation open backside passivation d) anisotropic deep etching opens "windows" in handle wafer Processing thin detectors 50 μm, 4 diodes, 10 mm 2 reverse current (pA) 700..850 pA/cm 2 Al

8. ECFA ILC Workshop, November 2005, ViennaLadislav Andricek, MPI für Physik, HLL Irradiation Issues D1 D2 S G1 G2 Cl Double pixel DEPFETs like in the main matrix from the latest production (Gate dielectrics: more than 200 nm) Radiation Effects (ionizing radiation) 1. postive oxide charge and postively charged oxide traps have to be compensated by a more negative gate voltage: negative shift of the theshold voltage (~t ox 2 ) 2. increased density of interface traps: higher 1/f noise and reduced mobility (g m )

9. ECFA ILC Workshop, November 2005, ViennaLadislav Andricek, MPI für Physik, HLL Threshold voltage shift GSF – National Research Center for Environment and Health, Munich 60 Co (1.17 MeV and 1.33 MeV) No annealing during irradiation  ~ 3 days irradiation Dose rate: ≈ 20 krad(SiO 2 )/h -∆V th (V) ∆Not (10 11 cm -2 ) "OFF" "ON" Dose (krad)

10. ECFA ILC Workshop, November 2005, ViennaLadislav Andricek, MPI für Physik, HLL Transconductance and subtreshold slope s=85mV/dec s=155mV/dec V th =-0.2V V th =-4.5V Literature: After 1Mrad 200 nm (SiO 2 ): N it ≈ 10 13 cm -2 300 krad  N it ≈2·10 11 cm -2 912 krad  N it ≈7·10 11 cm -2 No change in the transconductance g m

11. ECFA ILC Workshop, November 2005, ViennaLadislav Andricek, MPI für Physik, HLL Performance before irradiation 55 Fe Energy (eV) Counts/channel o non-irrad. double pixel DEPFET o L=7μm, W=25 μm o V thresh ≈-0.2V, V gate =-1V o I drain =41 μA o Drain current read out o time cont. shaping  =6 μs Noise ENC=2.3 e - (rms) at T>23 degC

12. ECFA ILC Workshop, November 2005, ViennaLadislav Andricek, MPI für Physik, HLL Performance after irradiation 55 Fe Energy (eV) Counts/channel o Irradiated double pixel DEPFET o L=7μm, W=25 μm o after 913 krad, 60 Co o V thresh ≈-4V, V gate =-5.3V o I drain =21 μA o Drain current read out o time cont. shaping  =6 μs Noise ENC=7.9 e - (rms) at T>23 degC

13. ECFA ILC Workshop, November 2005, ViennaLadislav Andricek, MPI für Physik, HLL Clear Gate after irradiation ( 60 Co) G1 G2 S D1 D2 Clear Gate Cl

14. ECFA ILC Workshop, November 2005, ViennaLadislav Andricek, MPI für Physik, HLL What's next in 2006?? 1. New production PXD5 -: bigger matrices -: better g q -: further improvement of clearing 2. Transfer thinning technology to production line -: qualify industrial partner for wafer bonding and top wafer thinning (engineered SOI Wafer) -: 150mm wafer -: produce diodes and mechanical samples as far as possible on main processing line

15. ECFA ILC Workshop, November 2005, ViennaLadislav Andricek, MPI für Physik, HLL New ILC DEPFET production  Main Device -: 512 x 512 pixels -: read out in both sides -: 24μm x 33μm pixel size -: array area: 17mm x 12.3mm -: chip area: ~ 21mm x 18mm  max. ILC width (outer layers) -: Array 2,2cm x 0,62cm  max. ILC length (layer 1) -: Array 0,5cm x 5cm + 128x128  "working horse" arrays + 128x64  design studies + single pixel, mini matrices, teststructures

16. ECFA ILC Workshop, November 2005, ViennaLadislav Andricek, MPI für Physik, HLL Thin test diodes, 150mm Wafer Top Wafer Handle Wafer a) oxidation and back side implant of top wafer b) wafer bonding and grinding/polishing of top wafer c) process  passivation open backside passivation d) anisotropic deep etching opens "windows" in handle wafer SOI Wafers ready! Material (Top and Handle): 150mm, FZ, 100 Ohm.cm Oxidation 230 nm Full sheet P-implant back side top wafer At TraciT, Grenoble: Wafer Bonding Annealing 1050 degC, 4h Grinding, CMP: 50 μm top wafer Edge treatment, polishing Top and Handle wafer Yield: No voids: 9 Wafer 1 void (<5mm): 7 Wafer More than one void: 4 Wafer  Continue processing at HLL (finished by end of 2005)

17. ECFA ILC Workshop, November 2005, ViennaLadislav Andricek, MPI für Physik, HLL In Summary.... So far:  Double Metal/Double Poly Technology established  Present Pixel size: 22x36 μm 2 – can go to ~ 20x20 µm 2, limited only by manufacturing equipment  Compact Linear DEPFETs show the expected excellent noise performance  Technology for thin (≤ 50μm ) detectors established (total budget 0.11% X 0 per layer)  Radiation tolerance against ionizing radiation demonstrated up to 1Mrad Advantages DEPFET:  Charge generation and first amplification in a fully depleted pixel cell  good Signal/Noise  No charge transfer needed:  better rad. tolerance against hadronic irradiation  Wafer scale arrays (6") possible:  easier module construction, less material  Charge collection in "OFF"-state, only one row active during readout:  low power consumption, less material for cooling  Production technology completely under control of detector designers and physicists We are ready to go for the next round!

18. ECFA ILC Workshop, November 2005, ViennaLadislav Andricek, MPI für Physik, HLL Workshop A Vertex Detector for the ILC - Physics and Technologies - May 28, 2006 - May 31, 2006 http://www.hll.mpg.de/~lca/ringberg