1. FPGA and ASIC Technology Comparison - 1 © 2009 Xilinx, Inc. All Rights Reserved Basic FPGA Architecture (Virtex-6) Clocking Resources

2. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 2 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 2 © 2009 Xilinx, Inc. All Rights Reserved Objectives After completing this module, you will be able to:  Detail the clocking resources available in the Virtex-6 FPGA  Specify the resources available in the Clock Management Tile (CMT)  Describe the basics of the PLL capabilities

3. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 3 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 3 © 2009 Xilinx, Inc. All Rights Reserved Clock Buffers MMCM Clock Wizard Automatic HDL code Virtex-6 Clock Management  Global clock buffers – High fanout clock distribution buffer  Regional clock distribution (low-skew)  I/O clock routing  Clock regions – Each clock region is 40 CLBs high and spans half the device  Clock management tile (CMT) – Two PLL-based Mixed-Mode Clock Managers (MMCMs) in each Clock Management Tile (CMT) – Up to nine CMTs per device – Performs frequency synthesis, clock de-skew, and jitter-filtering – High input frequency range (10-800 MHz)  Simple design creation through the Clocking Wizard

4. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 4 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 4 © 2009 Xilinx, Inc. All Rights Reserved MMCM Features  8 independently programmable clock outputs (O0-O6 and CLKFBOUT) – O0 to O3 and CLKFBOUT offer complementary outputs  Additional MMCM_ADV features – Clock input switching – Phase shift port – Dynamic Reconfiguration Port (DRP) – LOCK circuit enhanced to eliminate possibility of false LOCK  Both are easily customized with the Architecture Wizard MMCM able to implement both DCM and PLL functionality Each MMCM can be invoked with either the MMCM_BASE or MMCM_ADV primitive. SW takes care of unused ports on MMCM_BASE. CLKIN1 CLKFBIN CLKIN1 CLKFBIN CLKOUT CLKFBOUT CLKOUT CLKFBOUT MMCM_ADV CLKIN2 CLKINSEL DRP Phase Shift CLKIN2 CLKINSEL DRP Phase Shift RST LOCKED CLKIN1 CLKFBIN CLKIN1 CLKFBIN CLKOUT CLKFBOUT CLKOUT CLKFBOUT MMCM_BASE RST LOCKED

5. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 5 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 5 © 2009 Xilinx, Inc. All Rights Reserved Die View Clock Regions IO Columns Clock Spine and Column MMCM Tiles HROWs BUFIO (Single or Multi Region) BUFG in Center of Device BUFR BUFH Clocks in “Leaf” Region BUFH Mux Areas

6. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 6 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 6 © 2009 Xilinx, Inc. All Rights Reserved Virtex-6 FPGA Clock Distribution  Larger clock region – 40 CLBs high, 40 I/Os high – Same size as I/O bank – Half width of device – 6-18 regions per device  Resources per clock region – 12 global clock networks Driven by BUFH – 6 regional clock networks Driven by BUFR – 8 I/O clock networks per I/O column C L B 20 MMCMMMCM C L B 20 I O B 20 I O B 20 MMCMMMCM C L B 20 I O B 20 C L B 20 I O B 20

7. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 7 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 7 © 2009 Xilinx, Inc. All Rights Reserved Global Clocking  32 BUFGs reside in the center of the device  Driven by 8 global clock pins – There are also four clock-capable I/O pins per I/O bank Four differential or single-ended Global clock pins are not the only clock input resource  BUFGs can be driven by – Global clock inputs – Clock-capable inputs (inner I/O columns only) – MMCM outputs – Other BUFG – Interconnect – BUFR – GTX (recovered clock from GTX)  BUFG outputs can drive the vertical global clock spine  BUFGCTRL component implements – Glitch-free clock switching between two sources – Clock enable for disabling clocks BUFGCTRL O S1 S0 IGNORE0 IGNORE1 CE0 CE1 I1 I0

8. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 8 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 8 © 2009 Xilinx, Inc. All Rights Reserved Horizontal Clocking  12 BUFHs per clock region – You should not have to instantiate this  BUFH drives logic via horizontal global clock lines – BUFHs on left and right of vertical spine can be driven by the same CCIO or MMCM output  Driven by… – MMCM in the same region – BUFG via vertical clock spine – Clock-capable inputs in same horizontal row – Interconnect  Provides control of clocks routed into regions – Power saving by turning off or gating clocks to specific regions – Isolating logic into regions may require an Area Constraint BUFHCE I CE O BUFH I O

9. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 9 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 9 © 2009 Xilinx, Inc. All Rights Reserved Regional Clocking  Up to 4 BUFRs per clock region (varies by density) – 2 per I/O bank  Driven by… – Clock-capable inputs – Interconnect – GTX – MMCM high-performance clocks  Can drive… – Logic – IO logic – MMCM – BUFG  For medium- and high-performance clocks driving 1-3 regions (one above, self, and one below)  BUFR frequency can be divided by 1…8 BUFR ÷ CLR IO CE

10. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 10 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 10 © 2009 Xilinx, Inc. All Rights Reserved I/O Clocking  2 single-region BUFIOs and 2 multi-region BUFIOs in each I/O bank  Driven by… – Clock-capable inputs in the same I/O bank – MMCM outputs via high-performance paths  Can drive… – I/O logic in the same and adjacent I/O banks – BUFIO can drive logic resources only in the same I/O column  Intended for clocking high-speed I/O logic BUFIO I O

11. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 11 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 11 © 2009 Xilinx, Inc. All Rights Reserved Source-Synchronous Interfaces  I/O and regional clock networks combined with ISERDES/OSERDES provide powerful tools for creating source synchronous interfaces  BUFR is set to ÷N if interface is SDR, or ÷(N/2) if DDR – N can be 2 to 8 in SDR, and 2 to 10 in DDR Clock-Capable I/O (CCIO) I/O Clock Buffer (BUFIO) Conventional I/O (IO) Regional Clock Buffer (BUFR) N ISERDES CLK CLKDIV FPGA Fabric CLK Data IO CCIO BUFIO BUFR

12. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 12 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 12 © 2009 Xilinx, Inc. All Rights Reserved Performance Path Routing  4 performance paths driving each inner/outer left/right IO column  Driven by… – MMCM outputs O0-O3  Can drive… – BUFIO – BUFR – GTX  Powered by a regulated supply within each MMCM – This isolates the clocks from noise on Vccint – Cleanest path from MMCM to I/O columns – Lower jitter than any other routing  Software automatically places critical signals onto performance path routing, so don’t worry about controlling this route MMCM GTX IO

13. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 13 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 13 © 2009 Xilinx, Inc. All Rights Reserved Global Clocking Features Global Clock Inputs (IBUFG or IBUFGDS) Global Clock Multiplexers (BUFGCTRL) Flexibility  8 total – 8 differential (16 pins) or – 8 single-ended (8 pins)  32 total  Drive the global clock networks  Optional clock enable  Guaranteed glitchless clock switching Performance  Up to 800 MHz  Differential for maximum performance  High fanout (access to all clock loads in the FPGA)  Low skew  Short clock insertion delay

14. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 14 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 14 © 2009 Xilinx, Inc. All Rights Reserved I/O and Regional Clocking Clock-Capable I/Os I/O Clocks Regional Clocks Flexibility  Exist in all I/O columns  4 CCIOs per I/O bank – 4 differential (8 pins) or – 4 single-ended (4 pins)  Adjacent to HCLK row – 2 CCIOs above and below  Exist in all I/O columns  4 BUFIOs per I/O bank  Up to 8 I/O clock networks per I/O bank  Some clocks are local only; some can drive neighboring banks  Exist in all I/O columns  2 BUFRs per I/O bank  6 regional clock networks per region  Span up to three regions (one above and below)  Clock divider range from 1 to 8 Performance  800-MHz differential  500 MHz

15. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 15 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 15 © 2009 Xilinx, Inc. All Rights Reserved Virtex-6 Clock Network Summary Clock regions are 40 CLBs tall Clock regions match I/O banks 40 I/Os per bank 12 GCLKs (via BUFH) per region 2 BUFRs per I/O bank 2 single region BUFIOs 2 multi-region BUFIOs Clock regions span one half the die Four differential or single-ended clock capable inputs

16. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 16 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 16 © 2009 Xilinx, Inc. All Rights Reserved MMCM Features  Up to 9 CMTs per device – 2 MMCMs per CMT  Two software primitives – MMCM_BASE has only the basic ports – MMCM_ADV provides access to all ports  8 independently programmable clock outputs – O0 to O6 plus CLKFBOUT – O0 to O3 and CLKFBOUT true and complement outputs  Additional MMCM_ADV features – Clock input switching – Phase shift port CLKIN1 CLKFBIN CLKIN1 CLKFBIN CLKOUT CLKFBOUT CLKOUT CLKFBOUT MMCM_BASE RST LOCKED CLKIN1 CLKFBIN CLKIN1 CLKFBIN CLKOUT CLKFBOUT CLKOUT CLKFBOUT MMCM_ADV CLKIN2 CLKINSEL DRP Phase Shift CLKIN2 CLKINSEL DRP Phase Shift RST LOCKED

17. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 17 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 17 © 2009 Xilinx, Inc. All Rights Reserved MMCM Internals  Phase / frequency detector compares CLKIN with CLKFB – Accepts up to 650-MHz inputs – Adjusts the charge pump output voltage higher or lower – Charge pump controls the VCO frequency  Many different output frequencies can be generated – Fout = Fin * M / (D*O) – One M and one D value per MMCM – Each MMCM output can have its own O value – M: 1…64; D: 1…80; O: 1…128

18. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 18 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 18 © 2009 Xilinx, Inc. All Rights Reserved Extra MMCM Features  Fractional counters – Ability to configure O0 and CLKFBOUT as counters with 1/8 th granularity (e.g. 2.125, 2.250, 2.375, etc.) – O5 output is disabled when using this feature – Enables many more frequencies to be synthesized  Two methods of shifting phase – Static phase shift using time-shifted VCO outputs – Dynamic phase shift using the PS port to change the phase on the fly in increments of 1/56 of VCO period 0 45 90 135 180 225 270 315 VCO Outputs O0 O1 O2 O3 O4 O5 O6 CLKFBOUT

19. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 19 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 19 © 2009 Xilinx, Inc. All Rights Reserved Additional MMCM Signals  Complement outputs – O0-O3 of every MMCM have both true and complement outputs – Provide 180 degree phase shift  LOCKED – Signal showing that the MMCM has locked on to the input frequency  CLKINSTOPPED/FBSTOPPED – Status signals indicating that the input or feedback clocks have stopped running  PWRDWN (not shown) – Disable / Enable signal to the regulated supply of each MMCM Unused MMCMs draw power VCO LF CP PFD O0 CLKFB CLKIN1 CLKIN2 Routing Clock Switch D CLKINSTOPPED Lock CLKFBSTOPPED Stop Detect Lock Detect 9 O1 O2 O3 O4 O5 O6 M CLKFBOUT HOLD

20. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 20 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 20 © 2009 Xilinx, Inc. All Rights Reserved MMCM Connectivity  Many possible inputs to each MMCM – CCIO from inner I/O columns – Global clock inputs – BUFG – GTX clocks  MMCM outputs drive – BUFG – BUFH in same region – Performance paths to BUFIO and BUFR (not shown) MMCM Clock capable IO (Inner I/O Columns) GTX clocks Clock capable IO (Inner I/O Columns) HROW clock Global Clock inputs To BUFG From BUFG To BUFG CLKIN1 CLKIN2 CLKFBIN

21. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 21 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 21 © 2009 Xilinx, Inc. All Rights Reserved Clock Deskew  Use a BUFG on CLKFBOUT if a precise phase relationship between input clock and output clock is required – Most flexible solution but requires two global clock buffers  Remove the BUFG on CLKFBOUT if there is no need for a precise phase relationship – Frequency synthesis or jitter filtering only IBUFGBUFG CLKIN CLKFBIN CLKOUT0 CLKFBOUT

22. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 22 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 22 © 2009 Xilinx, Inc. All Rights Reserved MMCM-to-MMCM Connection IBUFG BUFG CLKIN CLKFBIN CLKOUT0 CLKFBOUT BUFG CLKIN CLKFBIN CLKOUT0 CLKFBOUT CLKOUT1 To Logic To Logic  MMCMs in the same CMT can be connected without the need for a global clock buffer – Output clock will not be aligned to input clock  More clock frequencies can thus be generated

23. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 23 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 23 © 2009 Xilinx, Inc. All Rights Reserved MMCM-to-MMCM Connection IBUFG BUFG CLKIN CLKFBIN CLKOUT0 CLKFBOUT BUFG CLKIN CLKFBIN CLKOUT0 CLKFBOUT CLKOUT1 To Logic To Logic BUFG To Logic  MMCMs in the same CMT can be connected without the need for a global clock buffer – Output of first MMCM connected to CLKIN of second MMCM – BUFG inserted from CLKFBOUT to CLKFBIN of the first MMCM to align output clock with input clock – CLKFBOUT of first MMCM can also drive logic  Enables more phase-aligned clock frequencies to be generated

24. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 24 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 24 © 2009 Xilinx, Inc. All Rights Reserved Example  Requirement – 33.3-MHz external oscillator controls 533-MHz data being generated by I/O logic (BUFIO) Large amount of logic at 66 MHz (BUFG) Small design at 54 MHz (BUFH) – Phase relationship between input clock and output clock is irrelevant  Solution – MMCM values M=16, D=1, O0=9.875, O1=1, O2=8 – Generates 54 MHz on clkout0 – O0 set to 9.875 using fractional counter 533 MHz on clkout1 66 MHz on clkout2 MMCM Performance Path CCIO BUFIO BUFH BUFG CLKIN1 CLKOUT0 CLKOUT1 CLKOUT2 CLKFBIN CLKFBOUT

25. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 25 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 25 © 2009 Xilinx, Inc. All Rights Reserved Summary  Clock regions = 40 CLBs, 40 IOBs in height – One or two I/O columns per region  32 global clock buffers (differential) – 8 global clock input pins (differential) – 12 global clocks per region  4 BUFIOs per I/O bank (differential) – 2 can drive adjacent I/O banks, others are local only  2 BUFRs per I/O bank – 6 regional clock networks – Can drive adjacent clock regions  The Clock Management Tile (CMT) has two Mixed-Mode Clock Managers (MMCMs) – Each MMCM includes a PLL – Jitter filtering and frequency synthesis capabilities

26. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 26 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 26 © 2009 Xilinx, Inc. All Rights Reserved Where Can I Learn More?  User Guides – Virtex-6 FPGA Clocking Resources User Guide Describes the complete clocking structures  Xilinx Education Services courses – www.xilinx.com/training www.xilinx.com/training Designing with the Virtex-6 and Spartan-6 Families course Xilinx tools and architecture courses Hardware description language courses Basic FPGA architecture, Basic HDL Coding Techniques, and other Free training videos!

27. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 27 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 27 © 2009 Xilinx, Inc. All Rights Reserved Xilinx is disclosing this Document and Intellectual Propery (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design. THE DESIGN IS PROVIDED “AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY. The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk. © 2009 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. Trademark Information