1. Kuang-Yu,Li 2013 IEE5011 –Autumn 2013 Memory Systems Duty Cycle Correctors (DCC) In GDDR5 SDRAM Kuang-Yu, Li Department of Electronics Engineering National Chiao Tung University li50916ku@gmail.com

2. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Outline Introduction Basics  DCC and GDDR5 Comparison  Analog and Digital DCC All-Digital DCC DCC in GDDR5 Conclusion 2

3. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Introduction GDDR5 AMD first shipped in 2008 Sony used in 2013 3

4. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Basic GDDR5 (1/4) 4

5. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Basic GDDR5 (2/4) Pre-fetch of 8 Array Bank Grouping New training and tracking New Clocking 5

6. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Basic GDDR5 (3/4) Data strobe signal (DQS)~>Write data clock(WCK) CK x 1, WCK x2, Data x4 6

7. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Basic GDDR5 (4/4) 7 [1]

8. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Basics DCC (1/3) Why do we need Duty-Cycle-Correctors ? Improve valid data window Reduce duty cycle error 8

9. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Basic DCC (2/3) Corrects input to 50% duty-cycle Two functions: Detect  define 50% boundary Correct  adjust edge until correct 9

10. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Basic DCC (3/3) Design : Location –on/off path Integration -embedded or not Locking time Operating frequency range Offset -comes from detector Implementation -analog or digital Other (power, area…) 10

11. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Analog DCC Simple negative feedback 11

12. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Analog DCC :Detector Integrating Error 12

13. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Analog DCC :Corrector Cross-coupled differential pair 13

14. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Digital DCC Simple negative feedback 14

15. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Digital DCC :Detector Detection Loop Time-mutiplexing between clocks Integrated error and amplified 15

16. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Digital DCC :Corrector Chargepump :offset adjusting 16

17. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Analog and Digital Comparison Digital DCC is preferred! Power,range,function,supply, mismatch 17 AnalogDigital DCC sharingXV Common mode Variation InsensitiveSensitive Correction rangeNarrowWide Power EfficientXV Manual overrideXV [2]

18. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li All-Digital DCC(ADDCC) Wide-range, high resolution Combined with DLL Low jitter and fast lock time Open loop scheme 18 DLL_out [3]

19. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li ADDCC: Timing Rising of DLL_out and Hclk Phase error ε,WSG delay α 19

20. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li ADDCC: Cycle Detector Dual delay line with WSG Overcoming trade-offs Small Overhead 20

21. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Measured Result 21 Process0.18um CMOS Operating frequency440MHz~1.5GHz Supply1.8V Duty cycle ratio50±2% Peak-to Peak jitter7ps@1.5GHz Maximum lock-in timeADDCC:5 cycles Area0.053mm 2 Power43mW@1.5GHz 69.9% --> 50.6% @440MHz

22. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li GDDR5 Clock Distribution P:PLL,G:Global Driver DQ Pad 22

23. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li DCC in GDDR5 Wide-range, fast-lock, offset tolerant [5]  Anti-harmonic binary search(ABS) CML and PLL in clock distribution 23

24. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li DCC in GDDR5 :Adjuster Between Rx and Driver Off clock-path –jitter free 4 phase clock 24 Step: 6ps Range: ±100ps

25. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li DCC in GDDR5 :Detector Switch,ABS circuit, 2 latches, comparator To adder based counter -> Adjuster 25

26. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li DCC in GDDR5 :Detection Methodology iclk vs. qclk and qclk vs. iclkb 26

27. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li DCC in GDDR5 :ABS Circuit Weighted Delay Cell and range adjuster Anti-harmonic and wide frequency range 27

28. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Measured Result Operating frequency and correction range 28

29. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Measured Result :Locking Time Five input clock ranges 29

30. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Measured Result :Locking process 30

31. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Chip Microphotograph 0.0017mm 2 31

32. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li DCC in GDDR5 Summary 32 Process54m CMOS triple-metal Operating frequency800MHz~3.5GHz (1.6 GHz~7 GHz) Supply1.5V Correction range-100ps ~ +100ps Step resolution6ps Lock-in timeMin:64 cycles Max:256 cycles Area0.017mm 2 Power4.5mW@3.5GHz

33. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Conclusion Digital DCC in state of the art DRAM design is necessary and important DCC in GDDR5 with wide-range fast-lock duty-cycle corrector with offset-tolerant capability WCK is up to 3.5GHz to sustain 7Gbps/pin 33

34. NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Reference [1] Kho, R,et.al, “A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques”, IEEE Journal of Solid-State Circuits, vol.45,no.1,pp120 - 133, Jan. 2010Kho, RSolid-State Circuits, vol.45,no.1 [2] L. Raghavan et.al, “Architectural Comparison of Analog and Digital Duty Cycle Corrector for High Speed I/O Link,” VLSI Design, pp 270-275,Jan.2010Raghavan et.al, VLSI Design [3] Dongsuk Shin et.al, “A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC”, ISSCC,pp184-185, Feb. 2007Dongsuk ISSCC [4] Shao-Ku Kao et.al, “All-Digital Fast-Locked Synchronous Duty-Cycle Corrector” IEEE Transactions on Circuits and Systems,vol.53,pp 1363 - 1367, Dec. 2006Shao-Ku KaoCircuits and Systems [5] Dongsuk Shin, Kwang-Jin Na et.al, “Wide-Range Fast-Lock Duty-Cycle Corrector with Offset-Tolerant Duty-Cycle Detection Scheme for 54nm 7Gb/s GDDR5 DRAM Interface,” Symposium on VLSI Circuits Digest of Technical Papers,pp 138-139, June 2009 [6] Kyung Hoon Kim et.al, “A 5.2Gb/p/s GDDR5 SDRAM with CML Clock Distribution Network”, ESSCIRC,pp194 - 197, Sept. 2008Kyung Hoon Kim ESSCIRC 34