1. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 1 1 Chapter 7 Logic Diagnosis

2. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 2 2 Outline  Introduction  Combinational Logic Diagnosis  Scan Chain Diagnosis  Logic BIST Diagnosis  Conclusion

3. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 3 3 What would you do when chips fail?  Is it due to design bugs?  If most chip fails with the same syndrome when running an application  Is it due to parametric yield loss?  Timing-related failure? –Insufficient silicon speed?  Noise-induced failure? –supply noise, cross-talk, leakage, etc.?  Lack of manufacturability? –inappropriate layout?  Is it due to random defects?  Via misalignment, Via/Contact void, Mouse bite,  Unintentional short/open wires, etc.

4. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 4 4 Problem: Fault Diagnosis Circuit Under Diagnosis (CUD) test patterns = expected response faulty response not equal ! Question: Where are the fault locations ? a chip with defects inside This chapter focuses more on diagnosis of defects or faults, not design bugs

5. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 5 5 Diagnosis For Yield Improvement Logic Diagnosis Defect Mechanisms A Set Of Potential Defect Locations Golden Reference Model Physical Failure Analysis Scanning Electronic Microscope (SEM) Focused Ion Beam (FOB) Tune the Manufacturing Process or Design for Yield Improvement Via void Mouse bite, etc.

6. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 6 6 Quality Metrics of Diagnosis  Success rate  The percentage of hitting at least one defect in the physical failure analysis  This is the ultimate goal of failure analysis  Diagnostic resolution  Total number of fault candidates reported by a tool  The perfect diagnostic resolution is 1  Though perfect resolution does not necessarily imply high hit rate  First-hit index  Used for a tool that reports a ranked list of candidates  Refers to the index of the first candidate in the ranked list that turns out to be a true defect site  Smaller first-hit index indicates higher accuracy  Top-10 hit  Used when there are multiple defects in the failing chip  The number of true defects in the top 10 candidates

7. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 7 7 Challenge Do whatever you want, but give me that damn bug(s) in less than 5 candidates. failure analysis people under time-to-market pressure

8. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 8 8 Supporting Circuitry memory Scan out MUX ff op_mode Logic Test input Supporting Circuitry: Makes Logic’s inputs controllable and outputs observable ff shift register

9. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 9 9 Design For Diagnosis More Supporting Circuitry Complexity Of Diagnosis Original Design Separated Logic & Memory interface circuitry Logic Design With Full-Scan Scan-chain

10. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 10 10 Possible Assumptions Used in Diagnosis  Stuck-At Fault Model Assumption  The defect behaves like a stuck-at fault  Single Fault Assumption  Only one fault affecting any faulty output  Logical Fault Assumption  A fault manifests itself as a logical error  Full-Scan Assumption  The chip under diagnosis has to be full-scanned Note: A diagnosis approach less dependent on the fault assumptions is more capable of dealing with practical situations.

11. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 11 11 Examples of Faults  Node Fault VDD A B A bridging GND C  Short Fault (Bridging) Most diagnosis algorithms performs at the gate level, trying to identify the troubling signals or cells   

12. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 12 12 Byzantine Open Fault  Definition of Byzantine Fault:  A fault that causes an ambiguous voltage level  ~ 2.5 v G2 G3 ‘1’ ‘0’ pseudo ‘0’ pseudo ‘1’ open fault G1

13. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 13 13 A Byzantine Node Type ABCZZfZf 00011 00100 01011 01100 1001~0 10100 11000 11100 faulty min-term C A bridging GND Z B C B VDD driver to ‘0’ driver to ‘1’ The faulty output could be ambiguous The faulty output could be ambiguous Truth Table

14. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 14 14 Fault Classification Fault in Logic IC Functional Fault Node Fault Open Fault Short Fault Byzantine Fault affects functionality Delay Fault Gate-Delay Fault Path-Delay Fault affects timing

15. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 15 15 Outline  Introduction  Combinational Logic Diagnosis  Cause-Effect Analysis  Effect-Cause Analysis  Chip-Level Strategy  Diagnostic Test Pattern Generation  Scan Chain Diagnosis  Logic BIST Diagnosis  Conclusion

16. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 16 16 Terminology  Device Under Diagnosis (DUD): The Failing Chip  Circuit Under Diagnosis (CUD): The Circuit Model  Failing Input Vector: Causes Mismatches input vector v xoooxxooox mismatched PO matched PO mismatched PO matched PO Failing chip Gate-level CUD

17. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 17 17 Cause-Effect Analysis  Fault dictionary (pre-analysis of all causes)  Records test response of every fault under the applied test set  Built by intensive fault simulation process  A chip is diagnosed (effect matching)  By matching up the failing syndromes observed at the tester with the pre-stored fault dictionary

18. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 18 18 Fault Dictionary Example Circuits Test vectors in terms of (a, b, c) v1v1 v2v2 v3v3 v4v4 v5v5 fault-free00001 f1f1 01111 f2f2 11101 f3f3 10011 f4f4 00100 f5f5 01101 (b) Full-response dictionary a b c g (a) Circuit under diagnosis Circuit under Diagnosis (c) Diagnostic tree { f 1, f 2, f 3, f 4, f 5 } output=0 v1v1 output=1 { f 1, f 4, f 5 } 01 v2v2 f4f4 { f 2, f 3 } 01 v2v2 f2f2 f3f3 { f 1, f 5 } 01 v4v4 f1f1 f5f5 A diagnosis session: traverse from a path from root to a leaf

19. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 19 19 Fault Dictionary Reduction – P&R Fault Output Response (z 1, z 2 ) t1t1 t2t2 t3t3 t4t4 f1f1 1 0 1 10 f2f2 0 001 00 f3f3 0 000 00 f4f4 0 1000 01 f5f5 000 1 f6f6 000 1 f7f7 1 0001 000 f8f8 1 111 11 (a) Full-response table (b) Pass-fail dictionary Fault Pass (0) or Fail (1) t1t1 t2t2 t3t3 t4t4 f1f1 1101 f2f2 1001 f3f3 1011 f4f4 1010 f5f5 1010 f6f6 1010 f7f7 1011 f8f8 0101 Fault ID Pass-fail + Extra outputs t1t1 t2t2 t3t3 t4t4 f1f1 1 10 11 f2f2 1 000 11 f3f3 1 00 1 f4f4 0 0 f5f5 01 0 f6f6 1 001 0 f7f7 01 01 f8f8 0 11 1 (c) P&R compression dictionary Response of z 1 Response of z 2

20. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 20 20 Detection Fault Dictionary Fault ID Output Response (z 1, z 2 ) t1t1 t2t2 t3t3 t4t4 f1f1 10 1110 f2f2 00 1100 f3f3 f4f4 0100 01 f5f5 0001 f6f6 0001 f7f7 10001000 f8f8 11 (a) Full-response table (b) Pass-fail dictionary Fault ID Pass (1) or Fail (0) t1t1 t2t2 t3t3 t4t4 f1f1 1101 f2f2 1001 f3f3 1011 f4f4 1010 f5f5 1010 f6f6 1010 f7f7 1011 f8f8 0101 Fault ID Detection information (Test ID : Output Vector) f1f1 t 1 :10 t 2 :10 t 4 :10; f2f2 t 1 :00 t 4 :00; f3f3 t 1 :00 t 3 :00 t 4 :00; f4f4 t 1 :01 t 3 :00; f5f5 t 1 :01 t 3 :01; f6f6 f7f7 t 1 :10 t 3 :10 t 4 :00; f8f8 t 2 :10 t 4 :11; (c) Detection dictionary failing output vectors

21. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 21 21 Outline  Introduction  Combinational Logic Diagnosis  Cause-Effect Analysis  Effect-Cause Analysis  Chip-Level Strategy  Diagnostic Test Pattern Generation  Scan Chain Diagnosis  Logic BIST Diagnosis  Conclusion

22. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 22 22 Terminology: Mismatched Output input vector v 0000000000 mismatched PO CUD 1000110001 failing chip failing PO Effect-cause analysis does not build fault dictionary It predicts fault locations by analyzing CUD from mismatch PO’s

23. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 23 23 Structural Pruning – Intersection or Union? (b) Cone union when there are multiple faults. z1z1 z2z2 z3z3 z1z1 z2z2 z3z3 z2z2 z3z3 z2z2 z3z3 (a) Cone intersection. primary inputs primary inputs Fault candidate set CUD

24. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 24 24 Backtrace Algorithm  Trace back from each mismatched PO  To find out suspicious faulty locations  Functional Pruning  During the traceback, some signals can be disqualified from the fault candidate set based on their signal values.  Rules  (1) At a controlling case (i.e., 0 for a NAND gate): Its fanin signals with non-controlling values (i.e., 1) are excluded from the candidate set.  (2) At a non-controlling case (i.e., 1 for a NAND gate): Every fanin signal remains in the candidate set.

25. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 25 25 Backtrace Example Target mismatched output 1 1 1 0 1 0 0 1 1 0 1 a b c d e f All suspicious fault locations are marked in red.

26. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 26 26 Terminology – Injection v f = ‘1’ xooxxxooxx v f = ‘0’ A mismatched output could be fixed by the injection! An injection at a signal f flips its current value which could create value-change events downstream. O: correct output X: failing output xooxo?xxooxo?x

27. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 27 27 Terminology – Curable Output  Diagnosis Criterion  A signal is more suspicious if it has more curable outputs v f = ‘1’ xooxxxooxx v f = ‘0’ xooooxoooo cured An injection at f fixes two mismatched outputs  Thus, f has two curable outputs ! O: correct output X: failing output

28. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 28 28 Terminology – Curable Vectors v f = ‘1’ xooxxxooxx v f = ‘0’ oooooooooo cured v is a curable vector by f  because an injection at f exists such that it cures all mismatches without creating new one Curable vector is a stronger diagnosis indicator than curable output !

29. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 29 29 Example of Curable Vector 1 1 1 f 1  0 0 1 0  1 1 0 1  0 x1x1 x2x2 x3x3 x4x4 cured 0101 x 1 = 0 x 2 = 1 x 3 = 1 x 4 = 1 1 failing (a) Failing Chip (b) Circuit Under Diagnosis

30. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 30 30 Why Curable Vector ?  Information theory  A less probable event contains more information  Curable output is an easy-to-satisfy criterion, high aliasing  Curable vector is a hard-to-satisfy criterion, low aliasing  Niche input vector –Is an failing input vector that activates only one fault –Likely to be a curable vector of certain signals –Few, but tells more about the real fault locations  Not all failing input vectors are equal !

31. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 31 31 Inject-and-Evaluate Paradigm input vectors design model failing chip response Calculate the no. of “curable vectors” of each signal Calculate the no. of “curable outputs” of each signal Sort the signals by the no. of “correctable vectors”, If tied, sort by the no. of “correctable outputs” ranking of each signal’s possibility of being a defect location Sorting Criteria

32. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 32 32 Detailed Computation – Inject-and-Evaluate Paradigm CUD netlist failing test vectors failing chip syndromes Set initial candidate set by structural pruning a list of ranked candidate signals for each failing input vector v { Step 1: perform logic simulation; Step 2: for each candidate signal f { Step 2.1: flip the value at f ; /* injection */ Step 2.2: run event-driven fault simulation; /*evaluation */ Step 2.3: calculate certain metrics /* ranking */ } Sort the candidate signals by the calculated metrics;

33. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 33 33 Reward-and-Penalty Heuristic Rank1: curable vector count Rank2 = (curable output count – 0.5 * new mismatched output count) 1 1 1 f 1  0 0 1 0  1 0 1 1  0 x1x1 x2x2 x3x3 x4x4 cured 0101 x 1 =0 x 2 =1 x 3 =1 x 4 =0 (a) Failing Chip. (b) Circuit Under Diagnosis. 1010 failing new mismatch passing

34. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 34 34 Targeting Bridging Faults w1w1 w2w2 A B C D bridging Even in a realistic bridging fault, there is only one victim at any time. This victim will expose his location by owning some curable vectors.

35. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 35 35 SLAT Paradigm A number of valid fault multiplets CUD failing input vectors failing chip response Phase 1: Finding SLAT (Single Location at A Time) vectors: (1) Fault simulation, (2) Output matching Phase 2: Finding valid fault multiplets (1) Finding single-fix candidates (2) Finding double-fix candidates (3) Finding triple-fix candidates, etc. Ref: SLAT (Single Location At a Time) paradigm [Bartenstein 2001] Note: A SLAT vector is a curable vector

36. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 36 36 Example: SLAT Paradigm Failing Input Vectors Signals in the CUD f1f1 f2f2 f3f3 f4f4 f5f5 f6f6 f7f7 v1v1 ** v2v2 *** v3v3 *** v4v4 ** v5v5 ** v6v6 ** v7v7 ** v8v8 ** v9v9 ** v 10 ** A mark * means the corresponding vector is a SLAT vector of the corresponding signal. (f 3 and f 5 ) is a valid fault multiplet

37. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 37 37 Outline  Introduction  Combinational Logic Diagnosis  Cause-Effect Analysis  Effect-Cause Analysis  Chip-Level Strategy  Diagnostic Test Pattern Generation  Scan Chain Diagnosis  Logic BIST Diagnosis  Conclusion

38. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 38 38 Structurally Dependent and Independent Faults inputs z1z1 z2z2 z3z3 fault f 2 fault f 1 fault f 3 Fault f 1 is an independent fault. Faults f 2 and f 3 are dependent faults. mismatched output

39. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 39 39 Dependency Graph z1z1 z2z2 z3z3 one connected component z1z1 z2z2 z3z3 fault f 2 fault f 1 Two independent faults, f 1 and f 2, lead to one diagnosis block. dependency graph Direct divide-and-Conquer does not work well !

40. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 40 40 Main Strategy : Detach-Divide-and-then-Conquer  Phase 1: Isolate Independent Faults  Search for prime candidates  Use word-level information  Phase 2: Locate Dependent Faults As Well  Perform partitioning  Aim at finding one fault in each block

41. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 41 41 Prime Candidates A signal f is a prime candidate if (1) All failing input vectors are partially curable by f (2) Curable-Output-Set(f) is not covered by any other’s f1 f2 f3 f1 & f2 are prime ! syndrome set 1 syndrome set 2

42. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 42 42 Fake Prime Candidates  Structurally Independent Faults  are often prime candidates  Fake Prime Candidates  are prime candidates that are NOT really faults - aliasing f1 f2 f3 f4 f5 Example: Dependent Double Faults f1 & f2 May create fake prime candidates {f1, f2, f3}.

43. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 43 43 Word-Level Registers and Outputs moduledesign( O1,...) output[31:0]O1; reg[31:0]R1, R2; reg[5:0]State... endmodule Word-Level Output: O1 Word-Level Registers: R1, R2, State Signals in a design are often defined in words. This property can be used to differentiate fake prime candidates from the real ones.

44. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 44 44 Word-Level Prime Candidates Original prime candidates: {f 1, f 2 } Word-level prime candidates {f 1, f 2 } Assumed original prime candidates: {f 3, f 4, f 5 } {f 4, f 5 } will be identified as fake  Final Word-level prime candidates {f 3 }

45. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 45 45 Efficiency of Using Word-Level Info.  Without word-level Information  2.4 real faults out of 72.3 candidates  With word-level Information  1.23 real faults out of 3.65 candidates # of candidatesOriginal After Filtering Filtering Ratio Prime Candidates 2.3751.2348.2 % Fake Prime Candidates 69.962.4296.5 %

46. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 46 46 Overall Flow Phase 1: (1) Find Word-Level Prime Candidates Phase 2: (1) Remove explained outputs and their fanin cones (2) Partition the rest model into blocks (3) Perform diagnosis for each block Rank candidates produced in phases 1 & 2 failing input vectors design model failing chip response

47. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 47 47 Grouping Using Dependency Graph X X X X X X X X X X X a b c e f g i j k c h i h f g j k a b c d e X X y z y z prime candidates An example with five faults One of them is identified as the prime candidate

48. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 48 48 Removed Explained Faulty Outputs X X X X X X X X X X X a b c e f g i j k d h X X y z prime candidates X X X X X X X X X X X a b c e f g i j k d h syndromes at y and z are fully explained

49. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 49 49 Grouping Example i h f g j k a b c d e X X X X X X X X X X X a b c e f g i j k d h Two independent diagnosis blocks Are successfully derived!

50. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 50 50 Summary  Strategy  (1) Search For Word-Level Prime Candidates  (2) Identify Independent Faults First  (3) Locate Dependent Faults As Well  Effectiveness  identify 2.98 faults in 5 signal inspections  find 3.8 faults in 10 signal inspections

51. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 51 51 Diagnostic Test Pattern Generation fault-free circuit c b a e d a2a2 d2d2 f g d 1 stuck-at 1 e d a2a2 d1d1 f g x d 2 stuck-at 0 a b c e d a1a1 a2a2 d1d1 d2d2 f g ⊕ ⊕ z/0 Model for differentiating vector generation DTPG helps to increase diagnostic resolution

52. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 52 52 Outline  Introduction  Combinational Logic Diagnosis  Scan Chain Diagnosis  Preliminaries  Hardware-Assisted Method  Signal-Profiling Based Method  Logic BIST Diagnosis  Conclusion

53. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 53 53 Scan Test and Diagnosis Flush test of scan chains (pumping random patterns and checking response) Pass or Fail? Test Combinational Logic PassFail Scan Chain Diagnosis Find failing scan chain(s) Classify fault types

54. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 54 54 Commonly Used Fault Types in Scan Chains Each fault could be permanent or intermittent. Scan Chain Faults Functional FaultsTiming Faults Setup-Time Violation Fault Stuck-at Bridging Slow-To-Rise Fault Slow-To-Fall Fault Hold-Time Violation Fault

55. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 55 55 A Stuck-At Fault In the Chain Effect: A killer of the scan-test sequence D Q input pins clock output pins D Q D Q Combinational Logic scan-input (SI) scan-output (SO) MUX scan-enable 11010100 00000000 s-a-0 ? All-0 syndrome

56. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 56 56 A Realistic Bridging Fault Model clock Scan input (SI) Scan output (SO) D Q MU X F1F1 F2F2 F3F3 F4F4   bridging (a) Bridging between a flip-flop and a logic cell. (b) Our bridging fault model. If(  ==1)  faulty =  else  faulty = F 2  faulty   F2F2

57. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 57 57 Potential Hold-Time Fault? (Negative Edge-Triggered Flip-Flop) CLK = high MasterSlave D Q Y CLK = low MasterSlave D Q Y CLK = low MasterSlave D Q Y faulty normal shut down too slowly

58. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 58 58 Example: Faulty Syndrome of a Scan Chain Fault TypeScan-In PatternObserved Syndrome Stuck-at-011001100110011000000000000000000 Stuck-at-111001100110011001111111111111111 Slow-to-Rise11001100110011001000100010001000 Slow-to-Fall11001100110011001101110111011100 SI (scan input pin) SO (scan output pin) A faulty flip-flop A scan chain A underlined bit in the observed image is failing. The rightmost bit goes into the scan first The rightmost bit gets out of the scan first

59. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 59 59 Augmentation of a Flip-Flop for Easy Diagnosis DFF MUX (From logic) (from scan chain) QD SC DFF MUX (From logic) (from scan chain) QD SC Invert (a) A normal scan flip-flop. (b) A modified scan flip-flop for easy inversion.

60. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 60 60 Fault Location via Inversion Operation SI SO Stuck-at-0 A scan chain (1)Original bitstream pattern = (1111111111111111) (2)After scan-in: snapshot image = (1111000000000000) (3)After inversion: snapshot image = (0000011111111111) (4)After scan-out: observed image = (0000011111111111) Fault-to-SOSI-to-fault The fault location is at the edge between 0’s and 1’s

61. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 61 61 Scan Chain Diagnosis Flow Circuit Under Diagnosis Diagnostic Test Sequence Generator Diagnostic Test Sequences Fault-Free Observed Images Signal Profiling Based Diagnosis Program Faulty FF’s location Observed Images Of Failing Chip Diagnosis Test Application

62. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 62 62 Definition: Snapshot Image input pins clock output pins Scan input (SI) Scan output (SO) Mission Logic 0 0 D Q 1 1 0 0 MUX x s-a-0 1 1 MUX Snapshot image: {(F 1, F 2, F 3, F 4 ) | (0, 1, 0, 1)} F1F1 F2F2 F3F3 F4F4 Def: A snapshot image is the combination of flip-flop values at certain time instance

63. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 63 63 Definition: Observed Image Def: An observed image is the scanned-out version of a snapshot image. input pins clock output pins Scan input (SI) Scan output (SO) Mission Logic 0 0 D Q 1 1 0 0 MUX x s-a-0 1 1 MUX Snapshot image: {(F 1, F 2, F 3, F 4 ) | (0, 1, 0, 1)} Observed image: {(F 1, F 2, F 3, F 4 ) | (0, 0, 0, 1)} F1F1 F2F2 F3F3 F4F4

64. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 64 64 Modified Inject-and-Evaluate Paradigm

65. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 65 65 Test Application: Run-and-Scan Step 1: Apply a test sequence from PI’s  Setting up a snapshot image at FF’s Step 2: Scan-out an observed image 0110 core logic x 0010 SO S-A-0 up-stream part will be distorted Less distorted image Test Sequence The fault location is embedded in the observed image

66. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 66 66 Signal Profiling A profile is the distribution of certain statistics of the flip-flops. Fault-free model faulty flip-flop Up-streamDown-stream 000.650.35 0.40.50.60.4 core logic Test Sequences fault-free image Scan Shifting 0.410.510.610.41 core logic perturbed image Failing chip x 0.40.50.60.4 similar different Fault-free profile Comparing failing profile with the fault-free profile  Could reveal the fault location

67. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 67 67 Profile Analysis Fault-free images (say 100 of them) Failing images (say 100 of them) report a ranked list of fault locations Derive the fault-free profile Derive the failing profile Derive the difference profile Perform filtering on the difference profile Perform edge detection to derive ranking profile A difference image = fault-free image ⊕ failing image Collected from tester

68. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 68 68 Example: Filtering & Edge Detection Signal-1 Frequency (%) Difference Profile Smooth ProfileRanking Profile Ranking (or suspicion) Profile Filtered Difference Profile Filtering & Edge Detection Scan Input  FF index  Scan Output

69. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 69 69 Computation of Average-Sum Filtering  (Average-sum filtering) Assume that the difference profile is given and denoted as D[i], where i is the index of a flip-flop. We use the following formula to compute a smoothed difference profile, SD[i]: SD[i] = 0.2*(D[i-2]+ D[i-1]+ D[i]+ D[i+1]+ D[i+2])

70. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 70 70 Computation of Edge Detection  The true location of the faulty flip-flop is likely to be the left- boundary of the transition region in the difference profile. To detect this boundary, we can use a simply edge detection formula defined below.  (Edge detection) On the smoothed difference profile SD[i], the following formula can be used to compute the faulty frequency of each flip-flop as a suspicious profile.

71. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 71 71 Summary of Scan Chain Diagnosis  Hardware Assisted  Extra logic on the scan chain  Good for stuck-at fault  Fault Simulation Based  To find a faulty circuit matching the syndromes [Kundu 1993] [Cheney 2000] [Stanley 2000]  Tightening heuristic  upper & lower bound [Guo 2001][Y. Huang 2005]  Use single-excitation pattern for better resolution [Li 2005]  Profiling-Based Method  Locate the fault directly from the difference profiles obtained by run-and-scan test  Applicable to bridging faults  Use signal processing techniques such as filtering and edge detection

72. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 72 72 Outline  Introduction  Combinational Logic Diagnosis  Scan Chain Diagnosis  Logic BIST Diagnosis  Overview  Interval-Based Method  Masking-Based Method  Conclusion

73. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 73 73 A Logic BIST Architecture MISR (Multiple-Input Signal Analyzer) Core Logic All flip-flops are assumed to be observable through scan chains. scan out (as the signature) PRPG (Pseudo-Random Pattern Generator)

74. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 74 74 Diagnosis for BISTed Logic  Diagnosis in a BIST environment requires  determining from compacted output responses which test vectors have produced a faulty response (time information)  determining from compacted output responses which scan cells have captured errors (space information)  The true fault location inside the logic  Can then be inferred from the above space and time information using previously discussed combinational logic diagnosis

75. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 75 75 Binary Search To Locate 1 st Failing Vector

76. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 76 76 Interval Unloading-Based Diagnosis

77. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 77 77 Deterministic Masking-Based Diagnosis MISR (Multiple-Input Signal Analyzer) Core Logic PRPG (Pseudo-Random Pattern Generator) (a) STUMP-based BIST architecture (b) Scan cell matrix Scan chain index (X) Scan slice index 7 6 5 4 3 2 1 Cell partition: X = {3,4} (chain set) Y = 2 (lower bound) Z = 6 (upper bound) Scan slice 12345678

78. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 78 78 Circuitry to Support Deterministic Masking MISR (Multiple-Input Signal Analyzer) Core Logic PRPG (Pseudo-Random Pattern Generator) 0 0 1 1 0 0 0 0 X Y 010 Z 110 ≧≦ Counter

79. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 79 79 A Search for Scan Cells Capturing Errors MISR (Multiple-Input Signature Register) Core Logic PRPG (Pseudo-Random Pattern Generator) Scan cells Capturing errors (Y, Z)=(1, 7) (Y, Z)=(1, 4)(Y, Z)=(5, 7) (Y, Z)=(1, 2)(Y, Z)=(3, 4)(Y, Z)=(5, 6)(Y, Z)=(7, 7) (Y, Z)=(3, 3)(Y, Z)=(4, 4) 9 BIST sessions (b) The search tree (a) Scan cells capturing errors in the fourth scan chain

80. EE141 VLSI Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 80 80 Conclusions  Logic diagnosis for combinational logic  Has been mature  Good for not just stuck-at faults, but also bridging faults  Scan chain diagnosis  Making good progress …  Fault-simulation-based, or signal-profiling based  Diagnosis of scan-based logic BIST  Hardware support is often required  Interval-unloading, or masking-based  Future challenges  Performance (speed) debug  Diagnosis for logic with on-chip test compression and decompression  Diagnosis for parametric yield loss due to nanometer effects