1. Testing of integrated circuits and design for testability J. Christiansen CERN - EP/MIC Jorgen.Christiansen@cern.ch

2. December 2003J.Christiansen/CERN2 Cost of finding failing chip

3. December 2003J.Christiansen/CERN3 Design verification testing

4. December 2003J.Christiansen/CERN4 Production testing

5. December 2003J.Christiansen/CERN5 Production yield

6. December 2003J.Christiansen/CERN6 Typical IC defects

7. December 2003J.Christiansen/CERN7 Reliability of integrated circuits Failure rate Time 1000 hours10 years Failing parts within first 1000 hours: ~1 % Burn-in testing : Heating up chips to 125 deg. accelerates 1000 hours period to approx. 24 hours. Static: power supply connected. Dynamic: Power + stimulation patterns. Functional test: Power + stimulation patterns + test. Temperature cycling: Continuous temperature cycling of chips to provoke temperature gradient induced faults. (Non matching thermal expansion coefficients). Badly designed component (electron migration, hot electron, corrosion, etc.) Infant mortality Wear out Electrical stress: Operation at elevated supply voltage

8. December 2003J.Christiansen/CERN8 What to test 100k – 100M

9. December 2003J.Christiansen/CERN9 Basic testing terms

10. December 2003J.Christiansen/CERN10 Fault models

11. December 2003J.Christiansen/CERN11 Problematic faults at transistor level

12. December 2003J.Christiansen/CERN12 Gate level (stuck at 0/1model) Bridge Stuck at 0 Stuck at 1 The gate level stuck at 0/1 is the dominantly used fault model for VLSI circuits, because of its simplicity. Opens and bridges not taken into account Fault coverage calculated by fault simulation are always calculated using the stuck at 0/1 model. Other more com- plicated fault models are to compute intensive for VLSI designs. Fault coverage = Number of faults detected by test pattern Total number of possible stuck at faults in circuit Open

13. December 2003J.Christiansen/CERN13 Testability

14. December 2003J.Christiansen/CERN14 Generation of test patterns Test vectors made by test engineer based on functional description and schematics. Proprietary test vector languages used to drive tester. (over the wall) Test vectors made by design engineer on CAE system. Subset of test patterns may be taken from design verification simulations. Generated by Automatic Test Pattern Generators ( ATPG). Requires internal scan path Pseudo random generated test patterns. Fault simulation calculates fault coverage.

15. December 2003J.Christiansen/CERN15 Fault simulation

16. December 2003J.Christiansen/CERN16 Test development with increased complexity SSI MSILSIVLSI pins/gate 1 0.1 0.01 0.001 Testability is decreasing drastically with increased integration level Cost (time) Complexity (time) 100 % 0 % Today Design Test development Digital Mixed analog/digital

17. December 2003J.Christiansen/CERN17 Memory testing Memory array Memory Row address Column address r o w a d r d e c col adr dec sense amp Data 0 100 0 0 0 0 0 1 1 1 1 1 1 1 Checker board Walking patterns 000 0000 0000 0000 000 0000 0000 0000 1 1 Test vectors = 4N Test vectors = 2N 2 64 k = 1.3 min. 256k = 22 min 1 M = 5.5 hours 100 MHz tester: 1 000 1 0 0 1 0 0 0 0 0 0 0 1 Address Test vectors = 2N Exhaustive test of a 1 M memory would take longer than estimated age of our universe. Large memory chips have built in redundant memory array columns enabling repair of failing memory cells. Algorithmic test patterns used.

18. December 2003J.Christiansen/CERN18 IC testers “ Cheap” = 500k$

19. December 2003J.Christiansen/CERN19 IC tester architectures

20. December 2003J.Christiansen/CERN20 Test vector timing formatting Some testers can do timing changes on the fly

21. December 2003J.Christiansen/CERN21 E-beam testing The reflection of an E-beam from a surface is influenced by voltage potential of the surface. Pattern generator Sync. Electrostatic shutter Chip Reflected charge collector Electron source Single point probing with very good timing resolution ( ~100ps ) Complete scan of chip to get voltage contrast picture at a specific time in pattern sequence. E-beam beam focusing e V using statistical averaging Difficult to use in modern technologies with many metal layers

22. December 2003J.Christiansen/CERN22 Scan Path testing

23. December 2003J.Christiansen/CERN23 Scan path testing

24. December 2003J.Christiansen/CERN24 Scan cells

25. December 2003J.Christiansen/CERN25 JTAG standard

26. December 2003J.Christiansen/CERN26 Boundary scan

27. December 2003J.Christiansen/CERN27 Connection of IC’s with JTAG TDI TDO TCK TMS TDI TDO TCK TMS TDI TDO TCK TMS TDI TDO TCK TMS Serial connection TDOTDI TCK TMS TDI TDO TCKTMS TDI TDO TCKTMS TDI TDO TCK TMS TDI TDO TCK TMS TDI TCK TMS1 TMS2 TDO Hybrid serial/parallel connection

28. December 2003J.Christiansen/CERN28 JTAG testing of mixed analog/digital IC’s Analog Digital TAP Consider analog part as being external and insert boundary scan registers between analog and digital. IEEE 1149.4 standard for test of analog parts has been defined. Principle: Two analog test busses to which internal nodes can be connected via analog multiplexers controlled from JTAG register

29. December 2003J.Christiansen/CERN29 JTAG testing of embedded on-chip memories Memory array Memory Address r o w a d r d e c col adr dec sense amp Data Each memory test vector must be shifted in/out serially Testing becomes very, very, very SLOW Use special Built In Self Test (BIST)

30. December 2003J.Christiansen/CERN30 JTAG Protocol Only 4 ( 5 ) pins used for JTAG interface TCK:Test clock Clock for loading control and test patterns TMS: Test mode select Selects mode of testing TDI:Test Data InputInput to shift registers TDO:Test Data OutOutput from shift registers

31. December 2003J.Christiansen/CERN31 JTAG Block diagram

32. December 2003J.Christiansen/CERN32 JTAG TAP controller TAP = Test Access Port

33. December 2003J.Christiansen/CERN33 JTAG scan cells

34. December 2003J.Christiansen/CERN34 JTAG test

35. December 2003J.Christiansen/CERN35 Built In Self Test (BIST)

36. December 2003J.Christiansen/CERN36 Simple pattern generation and verification

37. December 2003J.Christiansen/CERN37 BILBO = Built In Logic Block Observer

38. December 2003J.Christiansen/CERN38 Design for testability guidelines Use static logic. Make design completely synchronous. –use D flip-flops and not latches. –no clock gating. No internal clock generation. Prevent large counter like structures. Use scan path (JTAG). Use built in test of memories.

39. December 2003J.Christiansen/CERN39 And if you forget about testing