1. ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES Motivation and Introduction

2. 10/13/20152 Overview Motivation About the Course and the Instructor –ConductConduct –OutlineOutline –CoursepackCoursepack Introduction –VLSI realization processVLSI realization process –Contract between design house and fab vendorContract between design house and fab vendor –Test v/s verificationTest v/s verification –Need for testing: doing business, ideal v/s real testingNeed for testing: doing business, ideal v/s real testing –Levels of testing – rule of 10 (or 20)Levels of testing – rule of 10 (or 20) –Cost of manufacturingCost of manufacturing

3. 10/13/20153 Motivation Where do the manufacturing $ go? Overhead of one or two photomicrographs –What is test on a chip?What is test on a chip? Course conduct –Your responsibilities and mineYour responsibilities and mine Course outline Course material information –References and reading materialReferences and reading material

4. Motivation: Moore’s Law Complexity Growth of VLSI circuits Source (Copp, Int. AOC EW Conf., 2002) 10/13/20154

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6. Moore’s Law – Other Effects 10/13/20156

7. 7 Thermal Effect of Moore’s law  Moore’s law Greater packaging densities Higher power densities Higher temperature  Effects  Reliability  Performance  Power  Cooling cost

8. Introduction: Challenges under deep submicron technologies (Yao) Chip size decreases Power density increases Leakage power make it worseChip becomes hotter Source: Intel Source: Wang et al. ISPD2003

9. 10/13/20159 Microprocessor Cost per Transistor Cost of testing will EXCEED cost of design/manufacturing ( Source: ITR-Semiconductor, 2002)

10. 10/13/201510 VLSI Realization Process Determine requirements Write specifications Design synthesis and Verification Fabrication Manufacturing test Chips to customer Customer’s need Test development

11. Technology Directions: SIA Roadmap Year199920022005200820112014 Feature size (nm)18013090453222 Mtrans/cm 2 714-2647115284701 Chip size (mm 2 )170170-214235269308354 Signal pins/chip7681024 128014081472 Clock rate (MHz)6008001100140018002200 Wiring levels6-77-88-999-1010 Power supply (V)1.81.51.20.90.6 High-perf power (W)90130160170174183 Battery power (W)1.42.02.42.02.22.4 http://www.itrs.net/ntrs/publntrs.nsf Present and Future

12. 10/13/201512 Contract between a design house and a fab vendor Design is complete and checked (verified) Fab vendor: How will you test it? Design house: I have checked it and … Fab vendor: But, how would you test it? Desing house: Why is that important? It is between I and my clients – it is none of your businessDesing house: Why is that important? It is between I and my clients – it is none of your business Fab vendor – Sorry you can take your business some where else.Fab vendor – Sorry you can take your business some where else. complete the story and determine the reasons for the importance of test generation etc.

13. 10/13/201513 Contract between design … Hence: “Test” must be comprehensive It must not be “too long” Issues: Model possible defects in the process –Understand the processUnderstand the process Develop logic simulator and fault simulator Develop test generator Methods to quantify the test efficiency

14. 10/13/201514 Verification v/s Testing Definitions Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes. Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function. Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.

15. 10/13/201515 Verification v/s Testing Verifies correctness of design. Performed by simulation, hardware emulation, or formal methods. Performed once prior to manufacturing. Responsible for quality of design. Verifies correctness of manufactured hardware. Two-part process: –1. Test generation: software process executed once during design –2. Test application: electrical tests applied to hardware Test application performed on every manufactured device. Responsible for quality of devices.

16. 10/13/201516 Need for testing Functionality issue –Does the circuit (large or small) work?Does the circuit (large or small) work? Density issue –Higher density  higher failure probabilityHigher density  higher failure probability Application issue –Life critical applicationsLife critical applications Maintenance issue –Need to identify failed componentsNeed to identify failed components Cost of doing business What does testing achieve? –Discard only the “bad product”? – see next three slidesDiscard only the “bad product”? – see next three slides

17. 10/13/201517 Problems of Ideal Tests Ideal tests detect all defects produced in the manufacturing process. Ideal tests pass all functionally good devices. Very large numbers and varieties of possible defects need to be tested. Difficult to generate tests for some real defects. Defect-oriented testing is an open problem.

18. 10/13/201518 Real Tests Based on analyzable fault models, which may not map on real defects. Incomplete coverage of modeled faults due to high complexity. Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss. Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level.

19. 10/13/201519 Testing as Filter Process Fabricated chips Good chips Defective chips Prob(good) = y Prob(bad) = 1- y Prob(pass test) = high Prob(fail test) = high Prob(fail test) = low Prob(pass test) = low Mostly good chips Mostly bad chips

20. 10/13/201520 Levels of testing (1) Levels –ChipChip –BoardBoard –SystemSystem Boards put together System-on-Chip (SoC) –System in fieldSystem in field Cost – Rule of 10 –It costs 10 times more to test a device as we move to higher level in the product manufacturing processIt costs 10 times more to test a device as we move to higher level in the product manufacturing process

21. 10/13/201521 Levels of testing (2) Other ways to define levels – these are important to develop correct “fault models” and “simulation models”Other ways to define levels – these are important to develop correct “fault models” and “simulation models” –TransistorTransistor –GateGate –RTLRTL –FunctionalFunctional –BehavioralBehavioral –ArchitectureArchitecture Focus: Chip level testing – gate level design

22. 10/13/201522 Cost of Testing Design for testability (DFT) –Chip area overhead and yield reduction –Performance overhead Software processes of test –Test generation and fault simulation –Test programming and debugging Manufacturing test –Automatic test equipment (ATE) capital cost –Test center operational cost

23. 10/13/201523 Cost of Manufacturing Testing in 2010+ 0.5-1.0GHz, analog instruments,1024 digital pins: ATE purchase price –= $4.0M + 1,024 x $5,000 = $9.12M Running cost (five-year linear depreciation) –= Depreciation + Maintenance + Operation –= $1.80M + $0.185M + $1.5M –= $3.485M/year Test cost (24 hour ATE operation) –= $3.485M/(365 x 24 x 3,600) –= 11.05 cents/second

24. 10/13/201524 Roles of Testing Detection: Determination whether or not the device under test (DUT) has some fault. Diagnosis: Identification of a specific fault that is present on DUT. Device characterization: Determination and correction of errors in design and/or test procedure. Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT.

25. 10/13/201525 Summary About the course Expectations Why test? Cost issue – First look