Presentation is loading. Please wait.

Presentation is loading. Please wait.

UC San Diego / VLSI CAD Laboratory Incremental Multiple-Scan Chain Ordering for ECO Flip-Flop Insertion Andrew B. Kahng, Ilgweon Kang and Siddhartha Nath.

Published byValentine McLaughlin Modified over 9 years ago

Similar presentations

Presentation on theme: "UC San Diego / VLSI CAD Laboratory Incremental Multiple-Scan Chain Ordering for ECO Flip-Flop Insertion Andrew B. Kahng, Ilgweon Kang and Siddhartha Nath."— Presentation transcript:

1 UC San Diego / VLSI CAD Laboratory Incremental Multiple-Scan Chain Ordering for ECO Flip-Flop Insertion Andrew B. Kahng, Ilgweon Kang and Siddhartha Nath VLSI CAD LABORATORY, UC San Diego 32 nd IEEE/ACM International Conference on Computer-Aided Design November 20 th, 2013

2 -2- Outline Motivation Motivation Related Work Related Work Problem Formulations Problem Formulations IMSCO Flow IMSCO Flow Experimental Results Experimental Results Conclusions and Future Works Conclusions and Future Works

3 -3- Motivation Engineering Change Orders (ECOs) are IC design changes close to tapeout Engineering Change Orders (ECOs) are IC design changes close to tapeout –The testability of ECO logic is very challenging to the design schedule –To avoid loss of test coverage, ECO flip-flops (FFs) must be added for ECO logic

4 -4- Challenges for ECO FF Insertion ECO FFs should be distributed among existing scan chains to minimize test time ECO FFs should be distributed among existing scan chains to minimize test time Only a subset of existing scan chains will be compatible with ECO FF depending on clock domain Only a subset of existing scan chains will be compatible with ECO FF depending on clock domain Existing routing should be minimally perturbed to minimize impact on timing and existing routing congestion Existing routing should be minimally perturbed to minimize impact on timing and existing routing congestion ECO FF insertion flow should be automated ECO FF insertion flow should be automated –Manual ECO FF insertion near tapeout can cost days or weeks of design time

5 -5- Why Is The Problem Difficult? Large incremental wirelength (timing impact) Chain 1 Many edges perturbed (routing disturbance) Chain 1 Compromise between wirelength and #edges perturbed ECO FF Insertion Requires Good Heuristics How to tradeoff wirelength, test time, and impact to existing timing and routing?

6 -6- Our Work New Incremental Multiple-Scan Chain Ordering (IMSCO) formulation New Incremental Multiple-Scan Chain Ordering (IMSCO) formulation –Minimize test time (or scan chain depth) –Minimize incremental wirelength and congestion Affects setup timing slacks and routability of ECO changes Affects setup timing slacks and routability of ECO changes –Minimize disturbance of the existing routing and timing By minimizing number of edges that are modified By minimizing number of edges that are modified Develop heuristics for ordering scan chains based on Develop heuristics for ordering scan chains based on –Traveling Salesman Problem (TSP) Develop Incremental Scan Chain solver (ISC-solver) tool that Develop Incremental Scan Chain solver (ISC-solver) tool that –implements IMSCO heuristics to minimize test time, wirelength and routing disturbance –shows promising results

7 -7- Outline Motivation Motivation Related Work Related Work Problem Formulations Problem Formulations IMSCO Flow IMSCO Flow Experimental Results Experimental Results Conclusions and Future Works Conclusions and Future Works

8 -8- Relationship to TSP TSP: Given a set of cities, find a minimum-cost tour that visits every city exactly once TSP: Given a set of cities, find a minimum-cost tour that visits every city exactly once In IMSCO In IMSCO –City :: Scan FF –Cost :: Wirelength Our problem Our problem –Multiple salesmen –Multiple starting points  mTSP Scan chain ordering can be formulated as TSP

9 -9- Prior Works Two broad classifications Two broad classifications –Clustering and assignment of scan FFs –Ordering of assigned scan FFs Clustering and assignment Clustering and assignment –Elm et al. [2008] present partitioning heuristics to cluster scan FFs into scan chains –Seok et al. [2006] use placement information to divide a scan chain into multiple chains Ordering Ordering –Feuer and Koo [1983] first use TSP for scan chain optimization –Gupta et al. [2003] propose routing-driven and timing-driven methodology to order scan chains

10 -10- Outline Motivation Motivation Related Work Related Work Problem Formulations Problem Formulations IMSCO Flow IMSCO Flow Experimental Results Experimental Results Conclusions and Future Works Conclusions and Future Works

11 -11- Minimize Test Time Scan depth of chain 2 > scan depth of chain 1 Chain 1 Chain 2 Scan depth of chain 2 = scan depth of chain 1 Not good solution  Good solution Chain 1 Chain 2

12 -12- Minimize Incremental Wirelength Larger incremental wirelength Chain 1Chain 2 Not good solution  Good solution Chain 1 Chain 2 Smaller incremental wirelength  Potentially less impact to existing routing  We can minimize timing impact to existing scan chains  We can reduce routing congestion

13 -13- Minimize #Cut Edges Two cut edges disturb existing routing Chain 1 Not good solution  Good solution One cut edge reduces routing disturbance Chain 1  We can minimize the disturbance to existing routing (Major changes to existing routing may break previously-achieved timing closure)

14 -14- Outline Motivation Motivation Related Work Related Work Problem Formulations Problem Formulations IMSCO Flow IMSCO Flow Experimental Results Experimental Results Conclusions and Future Works Conclusions and Future Works

15 -15- Overall Flow Input: Original Scan Chains, ECO FFs, Constraints (1) Construction of Initial Clustering (Affinity) (2) Improvement of Initial Clustering (modified FM) (GainWL) (3) Selection of Multiple Cut Edges (k-way clustering, GainWL_byCE ) Output: Clustering and Ordering of ECO FFs with Multiple Cut Edges

16 -16- Initial Clustering Invoke TSP-solver (Concorde) Ordered list of ECO FFs per scan chain with min WL

17 -17- Improvement of Initial Clusters Chain 1 Chain 2 2 6 11 8 Chain 1 Chain 2 2 7 5 5 F

18 -18- Selection of Multiple Cut Edges We can reduce the incremental wirelength even more We can reduce the incremental wirelength even more We select multiple cut edges by using greedy k-way clustering We select multiple cut edges by using greedy k-way clustering –For ECO scan FFs in a given scan chain

19 -19- Outline Motivation Motivation Related Work Related Work Problem Formulations Problem Formulations IMSCO Flow IMSCO Flow Experimental Results Experimental Results Conclusions and Future Works Conclusions and Future Works

20 -20- Experimental Setup Develop ISC-solver to implement three-phase heuristics Develop ISC-solver to implement three-phase heuristics –Written C++ with several user configurations –Compiled with g++ 4.8.0 –Concorde as TSP-solver –Validated on 12-core HT Intel Xeon E5-2640 2.5GHz, 128GB RAM server Testcases Testcases –Industrial (from industry partners) –Artificial with our configurable scan instance generator –User options include layout size, #scan chains, #scan FFs per scan chain, #ECO FFs, congestion map, ….

21 -21- ISC-Solver User Parameters psd : Max % increase in scan depth allowed in chain psd : Max % increase in scan depth allowed in chain after ECO FFs insertion after ECO FFs insertion mel : Max edge length between scan FFs mel : Max edge length between scan FFs –To avoid use of high-leakage LVT cells lel : Min edge length between scan FFs lel : Min edge length between scan FFs –To avoid the need for excessive hold buffer insertion mce : Max #cut edges in each individual scan chain mce : Max #cut edges in each individual scan chain MCE : Max #cut edges in the entire design MCE : Max #cut edges in the entire design

22 -22- Option: psd psd   maximum scan depth  mel500 lel0 mce∞ MCE∞

23 -23- Option: mel mel   wirelength  psd0 lel0 mce∞ MCE∞

24 -24- Option: lel lel   wirelength  psd0 mel500 mce∞ MCE∞

25 -25- ISC-Solver Example Solutions mce is max #cut edges per scan chain ISC-solver reports smaller WL when mce increases

26 -26- ISC-Solver: Congestion-Awareness Congested regions Cut edges ISC-solver generates more cut edges to avoid high congestion area Non-congestion-aware Congestion-aware

27 -27- Comparison to Industrial Results Industrial testcase Industrial testcase –320 scan chains –634 ECO FFs –7 compatible scan chain groups 5.3% reduction in SD (no additional test time) from manual 5.3% reduction in SD (no additional test time) from manual 45.71% reduction of incremental WL compared to manual 45.71% reduction of incremental WL compared to manual RECOMMENDED SOLUTION !!

28 -28- Outline Motivation Motivation Related Work Related Work Problem Formulations Problem Formulations IMSCO Flow IMSCO Flow Experimental Results Experimental Results Conclusions and Future Works Conclusions and Future Works

29 -29- Conclusions and Future Works IMSCO provides automated flow to improve testability of ECO logic in SOC implementation flow IMSCO provides automated flow to improve testability of ECO logic in SOC implementation flow ISC-solver implements clustering, incremental clustering and ordering heuristics ISC-solver implements clustering, incremental clustering and ordering heuristics Compared to manual solutions, ISC-solver achieves Compared to manual solutions, ISC-solver achieves –5.3% of test time reduction –45.71% reduction in incremental wirelength Future works Future works –Code optimizations to speedup ISC-solver –Connections to operations research literature, e.g., via dynamic MDVRP with variable number of movable depots

30 Thank You!

31 -31- Affinity Calculation Scalability

32 -32- Option: mce mce   wirelength  mce   # of cut edges  psd0 mel5000 lel0 MCE∞

Download ppt "UC San Diego / VLSI CAD Laboratory Incremental Multiple-Scan Chain Ordering for ECO Flip-Flop Insertion Andrew B. Kahng, Ilgweon Kang and Siddhartha Nath."

Similar presentations

OCV-Aware Top-Level Clock Tree Optimization

OCV-Aware Top-Level Clock Tree Optimization
Timing Margin Recovery With Flexible Flip-Flop Timing Model

Timing Margin Recovery With Flexible Flip-Flop Timing Model
Minimum Implant Area-Aware Gate Sizing and Placement

Minimum Implant Area-Aware Gate Sizing and Placement
1 Advancing Supercomputer Performance Through Interconnection Topology Synthesis Yi Zhu, Michael Taylor, Scott B. Baden and Chung-Kuan Cheng Department.

1 Advancing Supercomputer Performance Through Interconnection Topology Synthesis Yi Zhu, Michael Taylor, Scott B. Baden and Chung-Kuan Cheng Department.
UC San Diego / VLSI CAD Laboratory NOLO: A No-Loop, Predictive Useful Skew Methodology for Improved Timing in IC Implementation Tuck-Boon Chan, Andrew.

UC San Diego / VLSI CAD Laboratory NOLO: A No-Loop, Predictive Useful Skew Methodology for Improved Timing in IC Implementation Tuck-Boon Chan, Andrew.
TPL-aware displacement-driven detailed placement refinement with coloring constraints Tao Lin and Chris Chu Iowa State University 1.

TPL-aware displacement-driven detailed placement refinement with coloring constraints Tao Lin and Chris Chu Iowa State University 1.
Background: Scan-Based Delay Fault Testing Sequentially apply initialization, launch test vector pairs that differ by 1-bit shift A vector pair induces.

Background: Scan-Based Delay Fault Testing Sequentially apply initialization, launch test vector pairs that differ by 1-bit shift A vector pair induces.
Evaluation of Placement Techniques for DNA Probe Array Layout Andrew B. Kahng 1 Ion I. Mandoiu 2 Sherief Reda 1 Xu Xu 1 Alex Zelikovsky 3 (1) CSE Department,

Evaluation of Placement Techniques for DNA Probe Array Layout Andrew B. Kahng 1 Ion I. Mandoiu 2 Sherief Reda 1 Xu Xu 1 Alex Zelikovsky 3 (1) CSE Department,
Boosting: Min-Cut Placement with Improved Signal Delay Andrew B. KahngSherief Reda CSE & ECE Departments University of CA, San Diego La Jolla, CA 92093.

Boosting: Min-Cut Placement with Improved Signal Delay Andrew B. KahngSherief Reda CSE & ECE Departments University of CA, San Diego La Jolla, CA
38 th Design Automation Conference, Las Vegas, June 19, 2001 Creating and Exploiting Flexibility in Steiner Trees Elaheh Bozorgzadeh, Ryan Kastner, Majid.

38 th Design Automation Conference, Las Vegas, June 19, 2001 Creating and Exploiting Flexibility in Steiner Trees Elaheh Bozorgzadeh, Ryan Kastner, Majid.
Power-Aware Placement

Power-Aware Placement
UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD.

UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD.
Architectural-Level Prediction of Interconnect Wirelength and Fanout Kwangok Jeong, Andrew B. Kahng and Kambiz Samadi UCSD VLSI CAD Laboratory

Architectural-Level Prediction of Interconnect Wirelength and Fanout Kwangok Jeong, Andrew B. Kahng and Kambiz Samadi UCSD VLSI CAD Laboratory
Local Unidirectional Bias for Smooth Cutsize-delay Tradeoff in Performance-driven Partitioning Andrew B. Kahng and Xu Xu UCSD CSE and ECE Depts. Work supported.

Local Unidirectional Bias for Smooth Cutsize-delay Tradeoff in Performance-driven Partitioning Andrew B. Kahng and Xu Xu UCSD CSE and ECE Depts. Work supported.
On Modeling and Sensitivity of Via Count in SOC Physical Implementation Kwangok Jeong Andrew B. Kahng.

On Modeling and Sensitivity of Via Count in SOC Physical Implementation Kwangok Jeong Andrew B. Kahng.
Placement Feedback: A Concept and Method for Better Min-Cut Placements Andrew B. KahngSherief Reda CSE & ECE Departments University of CA, San Diego La.

Placement Feedback: A Concept and Method for Better Min-Cut Placements Andrew B. KahngSherief Reda CSE & ECE Departments University of CA, San Diego La.
On Legalization of Row-Based Placements Andrew B. KahngSherief Reda CSE & ECE Departments University of CA, San Diego La Jolla, CA 92093

On Legalization of Row-Based Placements Andrew B. KahngSherief Reda CSE & ECE Departments University of CA, San Diego La Jolla, CA 92093
Fast and Area-Efficient Phase Conflict Detection and Correction in Standard-Cell Layouts Charles Chiang, Synopsys Andrew B. Kahng, UC San Diego Subarna.

Fast and Area-Efficient Phase Conflict Detection and Correction in Standard-Cell Layouts Charles Chiang, Synopsys Andrew B. Kahng, UC San Diego Subarna.
On-Line Adjustable Buffering for Runtime Power Reduction Andrew B. Kahng Ψ Sherief Reda † Puneet Sharma Ψ Ψ University of California, San Diego † Brown.

On-Line Adjustable Buffering for Runtime Power Reduction Andrew B. Kahng Ψ Sherief Reda † Puneet Sharma Ψ Ψ University of California, San Diego † Brown.
1 UCSD VLSI CAD Laboratory ISQED-2009 Revisiting the Linear Programming Framework for Leakage Power vs. Performance Optimization Kwangok Jeong, Andrew.

1 UCSD VLSI CAD Laboratory ISQED-2009 Revisiting the Linear Programming Framework for Leakage Power vs. Performance Optimization Kwangok Jeong, Andrew.

Similar presentations

Ads by Google