1. Unit I Testing and Fault Modelling

2. Syllabus
Introduction to testing – Faults in Digital Circuits – Modelling of faults – Logical Fault Models – Fault detection – Fault Location – Fault dominance – Logic simulation – Types of simulation – Delay models – Gate Level Event – driven simulation.

3. Basic Concept of Testing
Testing: To tell whether a circuit is good or bad
VDD
0/1
Related fields
Verification: To verify the correctness of a design
Diagnosis: To tell the faulty site
Reliability: To tell whether a good system will work correctly or not after some time.
Debug: To find the faulty site and try to eliminate the fault

4. Why Studying Testing? Economics! Reduce test cost (enhance profit)
Automatic test equipment (ATE) is extremely expensive
Shorten time-to-market
Market dominating or sharing
Guarantee IC quality and reliability
Defects detected in
Cost
Rule of Ten:
Cost to detect faulty
IC increases by an
order of magnitude
Wafer
0.01 – 0.1
Packaged chip
0.1 – 1
Board
1 – 10
System
10 – 100
Field
100 – 1000

5. Principle of Testing Testing typically consists of
Input Patterns
Output Response
-1011
11-00
-0-1-
01--0
0-101
Circuit
under
Test
(CUT)
1-001
0011-
-1101
1001-
01-11
Stored
Correct
Response
Comparator
Test Result
Testing typically consists of
Applying set of test stimuli (input patterns, test vectors) to inputs of circuit under test (CUT), and
Analyzing output responses
The quality of the tested circuits will depend upon the thoroughness of the test vectors

6. Introduction
Integrated Circuits (ICs) have grown in size and complexity since the late 1950’s
Small Scale Integration (SSI)
Medium Scale Integration (MSI)
Large Scale Integration (LSI)
Very Large Scale Integration (VLSI)
Moore’s Law: scale of ICs doubles every 18 months
Growing size and complexity poses many and new testing challenges
VLSI M S I
LSI S I

7. Importance of Testing
Moore’s Law results from decreasing feature size (dimensions)
from 10s of m to 10s of nm for transistors and interconnecting wires
Operating frequencies have increased from 100KHz to several GHz
Decreasing feature size increases probability of defects during manufacturing process
A single faulty transistor or wire results in faulty IC
Testing required to guarantee fault-free products

8. Importance of Testing (contd.)
N = # transistors in a chip
p = prob. (a transistor is faulty)
Pf = prob. (the chip is faulty)
Pf = 1- (1- p) N
If p = 10-6
N = 106
Pf = 63.2%

9. Difficulties in Testing
Fault may occur anytime
- Design
- Process
- Package
- Field
Fault may occur at any place
Vdd
Vss
VLSI circuit are large
- Most problems encountered in testing are NP-
complete
I/O access is limited

10. How to do testing From designer’s point of view: Circuit modeling
Fault modeling
Logic simulation
Fault simulation
Test generation
Design for test
Built-in self test
Synthesis for testability
Modeling
ATPG
Testable design

11. Levels of Structural Description
• Switch level
• Circuit level
VDD C C4 C1 B C3 C2 E
• Gate level
• Higher/ System level A E B G C D F

12. Why We Need Fault Models?
Fault models are needed for
test generation,
test quality evaluation and
fault diagnosis
To handle real physical defects is too difficult
The fault model should
reflect accurately the behaviour of defects, and
be computationably efficient
Usually combination of different fault models is used
Fault model free approaches (!)

13. Fault Modeling The effects of physical defects
Most commonly used fault model: Single stuck-at
fault E A
A s-a-1
A s-a-0
E s-a-1
E s-a-0
D s-a-1
D s-a-0
C s-a-1
C s-a-0
B s-a-1
B s-a-0
F s-a-1
F s-a-0
G s-a-1
G s-a-0
14 faults B G C D F
Other fault models:
- Break faults, Bridging faults, Transistor stuck-open faults,
Transistor stuck-on faults, Delay faults

14. Fault Modeling The effects of physical defects
Most commonly used fault model: Single stuck-at
fault E A
A s-a-1
A s-a-0
E s-a-1
E s-a-0
D s-a-1
D s-a-0
C s-a-1
C s-a-0
B s-a-1
B s-a-0
F s-a-1
F s-a-0
G s-a-1
G s-a-0
14 faults B G C D F
Other fault models:
- Break faults, Bridging faults, Transistor stuck-open faults,
Transistor stuck-on faults, Delay faults

15. Fault Modeling Fault modeling levels Hierarchical fault handling
Transistor level faults
Logic level faults
stuck-at fault model
bridging fault model
open fault model
delay fault model
Register transfer level faults
ISA level faults (MP faults)
SW level faults
Hierarchical fault handling
Functional fault modeling
Low-Level models
High-Level models

16. Faults and their Detection
Physical failures are manifested as electrical failures and are interpreted as faults on the logic level
Several physical defects may be mapped into few fault types
The main fault type is Stuck-at Fault
A fault is detected by a test pattern
Test pattern is an input combination that confirms the presence of the fault

17. Possible Defects
Two technologies, two physical defects map into the same stuck-at zero fault
Notation used - A SA0, or A/0

18. Detecting Stuck-at FaultsB Z
Fill in the blanks in
faulty response A/0 and A/1
Inputs FF
Faulty Response AB
Response
A/0
B/0
Z/0
A/1
B/1
Z/1 00 1 01 10 11 1 1

19. Detecting Stuck-at Faults

20. Detecting Stuck-at Faults
Inputs
Fault Free
Faulty Responses AB
Response
A/0
B/0
Z/0
A/1
B/1
Z/1 00 1 01 1 1 10 1 1 11 1 1 1 1

21. Structural and Functional Fault Modelingx1 a
Classification of fault models
x21
& x2
Fault models are: explicit and implicit
explicit faults may be enumerated
implicit faults are given by some characterizing properties
Fault models are: structural and functional:
structural faults are related to structural models, they modify interconnections between components
functional faults are related to functional models, they modify functions of components y 1
x22
& x3 b
Structural faults:
- line a is broken
- short between x2 and x3
Functional fault:
Instead of

22. Structural Logic Level Fault Modeling
Why logic fault models?
complexity of simulation reduces (many physical faults may be modeled by the same logic fault)
one logic fault model is applicable to many technologies
logic fault tests may be used for physical faults whose effect is not completely understood
they give a possibility to move from the lower physical level to the higher logic level
Stuck-at fault model:
Two defects:
Broken line
Bridge to ground x1 x1 1 1 x2 x2
Single model: Stuck-at-0 0V

23. Stuck-at Fault Properties
Fault equivalence and fault dominance:
A B C D Fault class
A/0, B/0, C/0, D/ Equivalence class
A/1, D/0
B/1, D/ Dominance classes
C/1, D/0 A B
& D C
Fault collapsing: 1 1
 1
 0 1
& 1
&
&
&
 1
 0
 0
 1
Equivalence
Dominance
Dominance
Equivalence

24. Fault Redundancy Hazard control circuitry: Error control circuitry: 1
01
&
Decoder
01
10 1 1
& 1
 1 
& 1 E
 0
Redundant AND-gate
Fault  0 is not testable
E  1 if decoder is fault-free
Fault  0 is not testable

25. Fault x42  0 is not testable
Fault Redundancy
Redundant gates (bad design): 1
& x1 x4 x3 y if
Fault x42  0 is not testable
x41
x42
x11
x12 1
& x1 x2 x4 x3 y
Faults at x2 are not testable, the node is redundant

26. Fault x42  0 is not testable Fault x12  1 is not testable
Fault Redundancy
Redundant gates (bad design): 1
& x1 x4 x3 y if
Fault x42  0 is not testable
x41
x42
x11
x12 1
& x1 x3 y
Fault x12  1 is not testable x4
x11
x12 if
Final result of optimization: x1 x4 y 1 x3

27. Fault Coverage (FC) FC = # faults detected # faults in fault list
Example: 1
6 stuck-at faults
( a0,a1,b0,b1,c0,c1 ) a 1 c b
Test
faults detected FC c1
a1,c1
a0,b0,c0
a0,b0,c0,c1
all
{(0,0)}
{(0,1)}
{(1,1)}
{(0,0),(1,1)}
{(1,0),(0,1),(1,1)}
16.67%
33.33%
50.00%
66.67%
100.00%

28. Wafer Yield (Chip Yield, Yield)
Good Chip
Faulty Chip
Defects
Wafer
Wafer yield = 12/22 = 0.55
Wafer yield = 17/22 = 0.77

29. Testing and Quality Shipped Parts IC Testing Fabrication Quality:
Yield:
Fraction of
good parts
Rejects
Shipped Parts
Quality:
Defective parts
per million (DPM)
Quality of shipped parts is a function of yield Y and the test (fault) coverage T
Defect level (DL, reject rate in textbook): fraction of shipped parts that are defective
Many delay faults can be detected by IDDQ testing because a circuit with a delay fault may imply that some transitions still exist in the circuit during steady state.

30. Fault Equivalence
Number of fault sites in a Boolean gate circuit = #PI + #gates + # (fanout branches).
Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2.
If faults f1 and f2 are equivalent then the corresponding faulty functions are identical.
Fault collapsing: All single faults of a logic circuit can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset.

31. Equivalence Rules
sa0 sa1
sa0
sa1
AND
NAND OR
NOR
WIRE
NOT
FANOUT

32. Equivalence Example sa0 sa1 Faults in red removed by equivalence
collapsing
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1 20
Collapse ratio = = 0.625 32

33. Fault Dominance
If all tests of some fault F1 detect another fault F2, then F2 is said to dominate F1.
Dominance fault collapsing: If fault F2 dominates F1, then F2 is removed from the fault list.
When dominance fault collapsing is used, it is sufficient to consider only the input faults of Boolean gates. See the next example.
In a tree circuit (without fanouts) PI faults form a dominance collapsed fault set.
If two faults dominate each other then they are equivalent.

34. Dominance Example All tests of F2 F1 s-a-1 001 F2 110 010 000 101 100
000
101
100
s-a-1 F2
011
Only test of F1
s-a-1
s-a-1
s-a-1
s-a-0
A dominance collapsed fault set

35. Dominance Example sa0 sa1 Faults in red removed by equivalence
collapsing
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
Faults in yellow
removed by
dominance
collapsing
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1 15
Collapse ratio = = 0.47 32

36. Classes of Stuck-at Faults
Following classes of single stuck-at faults are identified by fault simulators:
Potentially-detectable fault – Test produces an unknown (X) state at primary output (PO); detection is probabilistic, usually with 50% probability.
Initialization fault – Fault prevents initialization of the faulty circuit; can be detected as a potentially-detectable fault.
Hyperactive fault – Fault induces much internal signal activity without reaching PO.
Redundant fault – No test exists for the fault.
Untestable fault – Test generator is unable to find a test.

37. Transistor (Switch) Faults
MOS transistor is considered an ideal switch and two types of faults are modeled:
Stuck-open -- a single transistor is permanently stuck in the open state.
Stuck-short -- a single transistor is permanently shorted irrespective of its gate voltage.
Detection of a stuck-open fault requires two vectors.
Detection of a stuck-short fault requires the measurement of quiescent current (IDDQ).

38. Stuck-Open Example VDD A B C pMOS FETs Two-vector s-op test
Vector 1: test for A s-a-0
(Initialization vector)
Vector 2 (test for A s-a-1)
pMOS
FETs
VDD
Two-vector s-op test
can be constructed by
ordering two s-at tests A 1
Stuck-
open B C
1(Z)
Good circuit states
nMOS
FETs
Faulty circuit states

39. Stuck-Short Example VDD A B C pMOS FETs IDDQ path in faulty circuit
Test vector for A s-a-0
pMOS
FETs
VDD
IDDQ path in
faulty circuit A 1
Stuck-
short B
Good circuit state C
0 (X)
nMOS
FETs
Faulty circuit state

40. Types of Simulation Compiler driven simulation
Activity-directed simulation
Event-driven simulation

41. Delay Model Delay modeling for gates
Transport delay
Inertial delay
Delay modeling for functional elements
Delay modeling in RTLs
Other aspects of Delay modeling

42. Gate level Event driven simulation
Transition-Independent Nominal Transport delay
Other logic values
Other delay models