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Penn ESE535 Spring2015 -- DeHon 1 ESE535: Electronic Design Automation Day 2: January 26, 2015 Covering Work preclass exercise.

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Presentation on theme: "Penn ESE535 Spring2015 -- DeHon 1 ESE535: Electronic Design Automation Day 2: January 26, 2015 Covering Work preclass exercise."— Presentation transcript:

1 Penn ESE535 Spring2015 -- DeHon 1 ESE535: Electronic Design Automation Day 2: January 26, 2015 Covering Work preclass exercise

2 Feedback -- Piazza Last lecture –Average Pace 4 –everyone agreed was fast Posted followup on Piazza Identified a correction on assignment 2 on Piazza ….only 10 people signed up on Piazza Penn ESE535 Spring2015 -- DeHon 2

3 3 Today: Covering Problem Implement a “gate-level” netlist in terms of some library of primitives General Formulation –Make it easy to change technology –Make it easy to experiment with library requirements Evaluate benefits of new cells… Evaluate architecture with different primitives Behavioral (C, MATLAB, …) RTL Gate Netlist Layout Masks Arch. Select Schedule FSM assign Two-level, Multilevel opt. Covering Retiming Placement Routing

4 Penn ESE535 Spring2015 -- DeHon 4 Input 1.netlist (logical circuit) 2.library represent both in normal form: –nand gate –inverters

5 Penn ESE535 Spring2015 -- DeHon 5 Elements of a library - 1 INVERTER2 NAND23 NAND34 NAND45 Element/Area CostTree Representation (normal form) Example: Keutzer

6 Penn ESE535 Spring2015 -- DeHon 6 Elements of a library - 2 AOI21 4 AOI22 5 Element/Area Cost Tree Representation (normal form)

7 Penn ESE535 Spring2015 -- DeHon 7 Input Circuit Netlist ``subject DAG’’ Each wire is a network (net). Each net has a single source (the gate that drives it). In general, net may have multiple sinks (gates that take as input)

8 Penn ESE535 Spring2015 -- DeHon 8 Input Circuit Netlist ``subject DAG’’ A list of the nets (netlist) fully describes the circuit 0 nand 1 6 1 inv 2 2 nand 3 4 0 1 6 2 3 4 5

9 Penn ESE535 Spring2015 -- DeHon 9 Problem Statement into this library Find an ``optimal’’ (in area, delay, power) mapping of this circuit (DAG)

10 Penn ESE535 Spring2015 -- DeHon 10 Why covering now? Nice/simple cost model Problem can be solved well –somewhat clever solution General/powerful technique Show off special cases –harder/easier cases Show off things that make hard Show off bounding

11 Penn ESE535 Spring2015 -- DeHon 11 What’s the Problem? Trivial Covering subject DAG 7NAND2 (3) = 21 5INV (2) = 10 Area cost 31

12 Penn ESE535 Spring2015 -- DeHon 12 Preclass 1 Direct covering cost? 2346

13 Penn ESE535 Spring2015 -- DeHon 13 Preclass 3 & 4 Least Area Cover? (associated area?) –How did you get? 2346

14 Penn ESE535 Spring2015 -- DeHon 14 Cost Models

15 Penn ESE535 Spring2015 -- DeHon 15 Cost Model: Area Assume: Area in gates or, at least, can pick an area/gate –so proportional to gates e.g. –Standard Cell design –Standard Cell/route over cell –Gate array

16 16 Standard Cells Lay out gates so that heights match –Rows of adjacent cells –Standardized sizes Motivation: ease place and route Penn ESE535 Spring2015 -- DeHon 16

17 Penn ESE535 Spring2015 -- DeHon Standard Cell Area invnand3 All cells uniform height Width of channel determined by routing Cell area 17 Width of channel fairly constant?

18 Penn ESE535 Spring2015 -- DeHon 18 Cost Model: Delay Delay in gates –at least assignable to gates T wire << T gate T wire ~=constant –delay exclusively/predominantly in gates Gates have C out, C in lump capacitance for output drive delay ~ T gate + fanout  C in C wire << C in or C wire can lump with C out /T gate

19 Penn ESE535 Spring2015 -- DeHon 19 Logic Delay How would we calculate delay?

20 Penn ESE535 Spring2015 -- DeHon 20 Parasitic Capacitances

21 Penn ESE535 Spring2015 -- DeHon 21 Delay of Net

22 Penn ESE535 Spring2015 -- DeHon 22 Cost Model: Delay Delay in gates –at least assignable to gates T wire << T gate T wire ~=constant –delay exclusively/predominantly in gates Gates have C out, C in lump capacitance for output drive delay ~ T gate + fanout  C in C wire << C in or C wire can lump with C out /T gate F=22nm CMOS T gate (inv drive 4 inv)~=1ps T wire (300  m)~=1ps W gate ~=0.3  m

23 Penn ESE535 Spring2015 -- DeHon 23 Cost Models Why do I show you models? –not clear there’s one “right” model –changes over time –you’re going to encounter many different kinds of problems –want you to see formulations so can critique and develop own –simple cost models make problems tractable are surprisingly adequate –simple, at least, help bound solutions –may be wrong today…need to rethink

24 Penn ESE535 Spring2015 -- DeHon 24 Approaches

25 Penn ESE535 Spring2015 -- DeHon 25 Greedy work? Greedy = pick next locally “best” choice 2346

26 Penn ESE535 Spring2015 -- DeHon 26 Greedy In  Out 6 4 2

27 Penn ESE535 Spring2015 -- DeHon 27 Greedy In  Out 8 11

28 Penn ESE535 Spring2015 -- DeHon 28 Greedy Out  In 6 4 2

29 Penn ESE535 Spring2015 -- DeHon 29 Greedy Out  In 8 11

30 Penn ESE535 Spring2015 -- DeHon 30 But… 4 2 4 = 10

31 Penn ESE535 Spring2015 -- DeHon 31 Greedy Problem What happens in the future (elsewhere in circuit) will determine what should be done at this point in the circuit. Can’t just pick best thing for now and be done.

32 Penn ESE535 Spring2015 -- DeHon 32 Brute force? Pick a node (output) Consider –all possible gates which may cover that node –branch on all inputs after cover –pick least cost node

33 Penn ESE535 Spring2015 -- DeHon 33 Pick a Node

34 Penn ESE535 Spring2015 -- DeHon 34 Brute force? Pick a node (output) Consider –all possible gates which may cover that node –recurse on all inputs after cover –pick least cost node Explore all possible covers –can find optimum

35 Penn ESE535 Spring2015 -- DeHon 35 Analyze brute force? Time? Say P patterns, constant time to match each –(if patterns long could be > O(1)) P-way branch at each node… How big is tree? …exponential  O((P) depth )

36 Penn ESE535 Spring2015 -- DeHon 36 Structure inherent in problem to exploit? What structure exists?

37 Penn ESE535 Spring2015 -- DeHon 37 Structure inherent in problem to exploit? There are only N unique nodes to cover!

38 Penn ESE535 Spring2015 -- DeHon 38 Structure If subtree solutions do not depend on what happens outside of its subtree –separate tree –farther up tree Should only have to look at N nodes. Time(N) = N*P*T(match) –w/ P fixed/bounded  linear in N –w/ cleverness work isn’t P*T(match) at every node

39 Penn ESE535 Spring2015 -- DeHon 39 Idea Re-iterated Work from inputs Optimal solution to subproblem is contained in optimal, global solution Find optimal cover for each node Optimal cover: –examine all gates at this node –look at cost of gate and its inputs –pick least

40 Penn ESE535 Spring2015 -- DeHon 40 Work front-to-back

41 Penn ESE535 Spring2015 -- DeHon 41 Work Example (area) library 234545

42 Penn ESE535 Spring2015 -- DeHon 42 Work Example (area) library 234545 3 2 2 3

43 Penn ESE535 Spring2015 -- DeHon 43 Work Example (area) library 234545 3 2 2 3

44 Penn ESE535 Spring2015 -- DeHon 44 Work Example (area) library 234545 3 2 2 3 Consider all patterns

45 Penn ESE535 Spring2015 -- DeHon 45 Elements of a library - 1 INVERTER2 NAND23 NAND34 NAND45 Element/Area CostTree Representation (normal form) Example: Keutzer Copy to board

46 Penn ESE535 Spring2015 -- DeHon 46 Elements of a library - 2 AOI21 4 AOI22 5 Element/Area Cost Tree Representation (normal form)

47 Penn ESE535 Spring2015 -- DeHon 47 Work Example (area) library 234545 3 2 2 3 Consider all patterns

48 Penn ESE535 Spring2015 -- DeHon 48 Work Example (area) library 234545 3 2 2 3 3+3+2=8

49 Penn ESE535 Spring2015 -- DeHon 49 Work Example (area) library 234545 3 2 2 3 8

50 Penn ESE535 Spring2015 -- DeHon 50 Work Example (area) library 234545 3 2 2 3 8

51 Penn ESE535 Spring2015 -- DeHon 51 Work Example (area) library 234545 3 2 2 3 8 3+2=5

52 Penn ESE535 Spring2015 -- DeHon 52 Work Example (area) library 234545 3 2 2 3 8 5

53 Penn ESE535 Spring2015 -- DeHon 53 Work Example (area) library 234545 3 2 2 3 8 5 Consider All patterns

54 Penn ESE535 Spring2015 -- DeHon 54 Work Example (area) library 234545 3 2 2 3 8 5 3+5=8

55 Penn ESE535 Spring2015 -- DeHon 55 Work Example (area) library 234545 3 2 2 3 8 5 4

56 Penn ESE535 Spring2015 -- DeHon 56 Work Example (area) library 234545 3 2 2 3 8 5 4

57 Penn ESE535 Spring2015 -- DeHon 57 Work Example (area) library 234545 3 2 2 3 8 5 4 8+2+3=13

58 Penn ESE535 Spring2015 -- DeHon 58 Work Example (area) library 234545 3 2 2 3 8 5 4 13

59 Penn ESE535 Spring2015 -- DeHon 59 Work Example (area) library 234545 3 2 2 3 8 5 4 13 13+2=15

60 Penn ESE535 Spring2015 -- DeHon 60 Work Example (area) library 234545 3 2 2 3 8 5 4 13 3+2+4=9

61 Penn ESE535 Spring2015 -- DeHon 61 Work Example (area) library 234545 3 2 2 3 8 5 4 139

62 Penn ESE535 Spring2015 -- DeHon 62 Work Example (area) library 234545 3 2 2 3 8 5 4 139 9+4+3=16

63 Penn ESE535 Spring2015 -- DeHon 63 Work Example (area) library 234545 3 2 2 3 8 5 4 139 8+2+4+4=18

64 Penn ESE535 Spring2015 -- DeHon 64 Work Example (area) library 234545 3 2 2 3 8 5 4 139 16

65 Penn ESE535 Spring2015 -- DeHon 65 Work Example (area) library 234545 3 2 2 3 8 5 4 139 16 16+2=18

66 Penn ESE535 Spring2015 -- DeHon 66 Work Example (area) library 234545 3 2 2 3 8 5 4 139 16 13+5+4=22

67 Penn ESE535 Spring2015 -- DeHon 67 Work Example (area) library 234545 3 2 2 3 8 5 4 139 1618

68 Penn ESE535 Spring2015 -- DeHon 68 Work Example (area) library 234545 3 2 2 3 8 5 4 139 1618 18+3=21

69 Penn ESE535 Spring2015 -- DeHon 69 Work Example (area) library 234545 3 2 2 3 8 5 4 139 1618 9+4+4=17

70 Penn ESE535 Spring2015 -- DeHon 70 Work Example (area) library 234545 3 2 2 3 8 5 4 139 1618 8+2+4+5=19

71 Penn ESE535 Spring2015 -- DeHon 71 Work Example (area) library 234545 3 2 2 3 8 5 4 139 1618 17

72 Penn ESE535 Spring2015 -- DeHon 72 Optimal Cover library 234545 3 2 2 3 8 5 4 139 1618 17

73 Penn ESE535 Spring2015 -- DeHon 73 Optimal Cover library 234545 3 2 2 3 8 5 4 139 1618 17 Much better than 31!

74 Penn ESE535 Spring2015 -- DeHon 74 Note There are nodes we cover that will not appear in final solution.

75 Penn ESE535 Spring2015 -- DeHon 75 “Unused” Nodes library 234545 3 2 2 3 8 5 4 13 9 1618 17

76 Penn ESE535 Spring2015 -- DeHon 76 Dynamic Programming Solution Solution described is general instance of dynamic programming Require: –optimal solution to subproblems is optimal solution to whole problem –(all optimal solutions equally good) –divide-and-conquer gets same (finite/small) number of subproblems Same technique used for instruction selection in code generation for processors

77 Penn ESE535 Spring2015 -- DeHon 77 Delay Similar –Delay(node) = Delay(gate)+Max(Delay(input))

78 Penn ESE535 Spring2015 -- DeHon 78 DAG DAG = Directed Acyclic Graph –Distinguish from tree (tree  DAG) –Distinguish from cyclic Graph –DAG  Directed Graph (digraph) treeDAG Digraph

79 Penn ESE535 Spring2015 -- DeHon 79 Trees vs. DAGs Optimal for trees –why? Delay Area

80 Penn ESE535 Spring2015 -- DeHon 80 Not optimal for DAGs Why?

81 Penn ESE535 Spring2015 -- DeHon 81 Not optimal for DAGs Why? 1+1+1=3

82 Penn ESE535 Spring2015 -- DeHon 82 Not optimal for DAGs Why? 1+1+1=3 3+3+1=7 ?

83 Penn ESE535 Spring2015 -- DeHon 83 Not Optimal for DAGs (area) Cost(N) = Cost(gate) +  Cost(input nodes) think of sets cost is magnitude of set union Problem: minimum cost (magnitude) solution isn’t necessarily the best pick –get interaction between subproblems –subproblem optimum not global...

84 DAG Example Cover with 3 input gates Penn ESE535 Spring2015 -- DeHon 84

85 DAG Example Cover with 3 input gates Penn ESE535 Spring2015 -- DeHon 85

86 Penn ESE535 Spring2015 -- DeHon 86 Not Optimal for DAGs Delay: –in fanout model, depends on problem you haven’t already solved (delay of node depends on number of uses)

87 Penn ESE535 Spring2015 -- DeHon 87 What do people do? Cut DAGs at fanout nodes optimally solve resulting trees Area –guarantees covered once get accurate costs in covering trees, made “premature” assignment of nodes to trees Delay –know where fanout is

88 Penn ESE535 Spring2015 -- DeHon 88 Bounding Tree solution give bounds (esp. for delay) –single path, optimal covering for delay –(also make tree by replicating nodes at fanout points) no fanout cost give lower bounds –know you can’t do better delay lower bounds useful, too –know what you’re giving up for area –when delay matters

89 Penn ESE535 Spring2015 -- DeHon 89 (Multiple Objectives?) Like to say, get delay, then area –won’t get minimum area for that delay –algorithm only keep best delay –…but best delay on off critical path piece not matter …could have accepted more delay there –don’t know if on critical path while building subtree –(iterate, keep multiple solutions)

90 Penn ESE535 Spring2015 -- DeHon 90 Many more details... Implement well Combine criteria …but now you know the main idea

91 Penn ESE535 Spring2015 -- DeHon 91 Big Ideas simple cost models problem formulation identifying structure in the problem special structure characteristics that make problems hard bounding solutions

92 Penn ESE535 Spring2015 -- DeHon 92 Admin Reading for today: canvas Reading for Wednesday: –online/ACM DL –Highly relevant to assignment 3..6 Office Hour: T4:30pm –Or make an appointment


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