1. Voltage Divider Bias ELEC 121

2. January 2004ELEC 1212 BJT Biasing 3 For the Voltage Divider Bias Configurations Draw Equivalent Input circuit Draw Equivalent Output circuit Write necessary KVL and KCL Equations Determine the Quiescent Operating Point –Graphical Solution using Loadlines –Computational Analysis Design and test design using a computer simulation

3. January 2004ELEC 1213 Voltage-divider bias configuration

4. January 2004ELEC 1214 Voltage Divider Input Circuit Approximate Analysis The Approximate method may be used only when R 2 .1  R E Under these conditions R E does not significantly load R 2 and it is effect may be ignored: I B << I 1 and I 2 and I 1  I 2 Therefore: We may apply KVL to the input, which gives us: -V B + V BE + I E R E = 0 Solving for I E we obtain:

5. January 2004ELEC 1215 Input Circuit Exact Analysis The Exact Analysis method is always valid must be used when R 2 >.1  R E Perform Thevenin’s Theorem using the transistor as the load Open the base lead of the transistor, and the Voltage Divider bias circuit is: Calculate R TH We may apply KVL to the input, which gives us: -V TH + I B R TH + V BE + I E R E = 0 Since I E = (  + 1) I B

6. January 2004ELEC 1216 Redrawing the input circuit for the network

7. January 2004ELEC 1217 Determining V TH

8. January 2004ELEC 1218 Determining R TH

9. January 2004ELEC 1219 The Thévenin Equivalent Circuit Note that V E = V B – V BE and I E = (  + 1)I B

10. January 2004ELEC 12110 Input Circuit Exact Analysis We may apply KVL to the input, which gives us: -V TH + I B R TH + V BE + I E R E = 0 Since I E = (  + 1) I B

11. January 2004ELEC 12111 Collector-Emitter Loop

12. January 2004ELEC 12112 Collector-Emitter (Output) Loop Applying Kirchoff’s voltage law: - V CC + I C R C + V CE + I E R E = 0 Assuming that I E  I C and solving for V CE : I C = V CC – V CE – (R E + R C ) Solve for V E : V E = I E R E Solve for V C : V C = V CC - I C R C or V C = V CE + I E R E Solve for V B : V B = V CC - I B R B or V B = V BE + I E R E

13. January 2004ELEC 12113 Voltage Divider Bias Example 1

14. January 2004ELEC 12114 Voltage Divider Bias Example 2

15. January 2004ELEC 12115 Design of CE Amplifier with Voltage Divider Bias 1.Select a value for V CC 2.Determine the value of  from spec sheet or family of curves 3.Select a value for I CQ 4.Let V CE = ½ V CC (typical operation, 0.4 V CC ≤ V C ≤ 0.6 V CC ) 5.Let V E = 0.1 V CC (for good operation, 0.1 V CC ≤ V E ≤ 0.2 V CC ) 6.Calculate R E and R C 7.Let R 2 ≤ 0.1  R E (for this calculation, use low value for  ) 8.Calculate R 1

16. January 2004ELEC 12116 CE Amplifier Design Design a Common Emitter Amplifier with Voltage Divider Bias for the following parameters: V CC = 24V I C = 5mA V E =.1V CC V C =.55V CC  = 135

17. January 2004ELEC 12117

18. January 2004ELEC 12118 CE Amplifier Design

19. January 2004ELEC 12119 CE Amplifier Design Voltage Divider Bias

20. January 2004ELEC 12120 Voltage Divider Bias with Dual Power Supply

21. January 2004ELEC 12121 Voltage Divider Bias with Dual Power Supply Input Circuit Find V TH and R TH

22. January 2004ELEC 12122 Voltage Divider Bias with Dual Power Supply Output Circuit

23. January 2004ELEC 12123 Voltage Divider Bias with Dual Power Supply

24. PSpice Simulation

25. January 2004ELEC 12125 PSpice Bias Point Simulation

26. January 2004ELEC 12126 PSpice Simulation for DC Bias

27. January 2004ELEC 12127 PSpice Simulation for DC Sweep

28. January 2004ELEC 12128 PSpice Simulation for DC Sweep The response of V CE demonstrates that it reaches a peak value near the Q point and then decreases The response of V C demonstrates rises rapidly towards the Q Point and then increases gradually towards a maximum value

29. January 2004ELEC 12129 Simulation Settings for AC Sweep

30. January 2004ELEC 12130 Probe Output for AC Sweep