1. CMOS Digital Integrated Circuits
Lec 10
Combinational CMOS Logic Circuits

2. Combinational vs. Sequential Logic
Out
Combinational
Logic
circuit In
Combinational
Logic
circuit In
Out
State
Combinational
Sequential
The output is determined by
Current inputs
Previous inputs
The output is determined only by
Current inputs
Output = f(In)
Output = f(In, Previous In)

3. Static CMOS Circuit
At every point in time (except during the switching transients) each gate output is connected to either VDD or VSS via a low-resistive path
The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods).
This is contrasted to the dynamic circuit class, which relies on temporary storages of signal values on the capacitance of high impedance circuit nodes.

4. Static CMOS … … VDD In1 In2 Pull Up Network (PUN) InN f(In1,In2,…InN)
pMOS
Network
In2 …
Pull Up Network (PUN)
InN
f(In1,In2,…InN)
In1
nMOS
Network
In2 …
Pull Down Network (PDN)
InN
PUN and PDN are dual logic networks
The complementary operation of a CMOS gate
The nMOS network (PDN) is on and the pMOS network (PUN) is off
The pMOS network is on and the nMOS network is off.

5. NMOS Transistors Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
NMOS Transistors pass a “strong” 0 but a “weak” 1 X Y A B
Y = X if A and B=AB
Y = X if A OR B=A+B

6. PMOS Transistors Series/Parallel Connection
PMOS switch closes when switch control input is low
PMOS Transistors pass a “strong” 1 but a “weak” 0 A B
Y = X if A AND B = A+B X Y A B X
Y = X if A OR B = AB Y

7. Threshold Drops VDD VDD PUN S D VDD D S 0  VDD 0  VDD - VTn VGS CL
PDN
VDD  |VTp|
VGS D S CL CL
VDD S D

8. CMOS Logic Style  PUN is the DUAL of PDN
(can be shown using DeMorgan’s Theorem’s)
The complementary gate is inverting
AND = NAND + INV 

9. Example Gate: NAND

10. CMOS NOR2 Two-Input NOR Gate
IDB,p
IDA,p ID
IDA,n
IDB,n

11. CMOS NOR2 Threshold Calculation (1/3)
Basic Assumptions
Both input A and B switch simultaneously (VA = VB)
The device sizes in each block are identical. (W/L)n,A = (W/L)n,B , and (W/L)p,A = (W/L)p,B
The substrate-bias effect for the PMOS is neglected
Vth Calculation
By definition, VA = VB = Vout = Vth. The two NMOS transistors are saturated because VGS = VDS,
ID = IDA,n + IDB,n = kn(Vth-VT,n)2
PMOS-B operates in the linear region, and PMOS-A is in saturation for Vin = Vout, B A F
VDD
IDA,p
IDB,p
IDA,n
IDB,n

12. CMOS NOR2 Threshold Calculation (2/3)
Since IDA,p = IDB,p = ID, we have
Combine the above equations, we obtain
which is different with the expression of Vth(INV)

13. CMOS NOR2 Threshold Calculation (3/3)
If kn = kp and VT,n = |VT,p| , Vth(INV) = VDD/2. However,
Equivalent-Inverter Approach (both inputs are identical)
The parallel connected nMOS transistors can be represented by a nMOS transistor with 2kn.
The series connected pMOS transistors can be represented by a pMOS transistor with kp/2.
Vin
VDD
Vout
kp/2
2kn

14. CMOS NOR2 Equivalent-Inverter Approach
Therefore
To obtain a switching threshold voltage of VDD/2 for simultaneous switching, we have to set VT,n = |VT,p| and kp=4kn
Parasitic Capacitances and Simplified Equivalent Circuit: See Fig in Kang and Leblebici.
The total lumped load capacitance is assumed to be equal to the sum of all internal capacitances in the worst case.

15. CMOS NAND2 Two-Input NAND Gate

16. CMOS NAND2 Threshold Calculation
Assume the device sizes in each block are identical, (W/L)n,A = (W/L)n,B , and (W/L)p,A = (W/L)p,B, and by the similar analysis to the one developed for the NOR2 gate, we have
To obtain a switching threshold voltage of VDD/2 for simultaneous switching, we have to set VT,n = |VT,p| and kn=4kp

17. Layout of Simple CMOS Logic Gates (1/2)V DD
Out In
Inverter
GND

18. Layout of Simple CMOS Logic Gates (2/2)V DD
GND B
2-input NAND gate

19. Stick Diagram (1/2) Basic Elements
Does not contain any information of dimensions.
Represent relative positions of transistors
Basic Elements
Rectangle: Diffusion Area
Solid Line: Metal Connection
Circle: Contact
Cross-Hatched Strip: Polysilicon In
Out V DD
GND
INV A B
NAND2

20. Stick Diagram (2/2) In
Out V DD
GND
INV A B
NAND2

21. Complex CMOS Gates Functional Design (1/3)
OR operations are performed by parallel-connected drivers.
AND operations are performed by series-connected drivers.
Inversion is provided by the nature of MOS circuit operation.
The realization of pull-down network is based on the same basic design principle examined earlier.
The pMOS pull-up network must be the dual network of the nMOS pull-down network.
One method systematically derives the pull-up network directly form the pull-down network. This method constructs the dual graph of the network. The pull-down network graph has nodes for circuit nodes and arcs for nFETs with the each arc labeled with the literal on the input to the corresponding nFET.

22. Complex CMOS Gates Functional Design (2/3)
To construct a graph and pull-up network from a pull-down network
Insert a node in each of the enclosed areas within the pull-down network graph.
Place two nodes outside of the network separated by arcs from GND and OUT.
Connect pairs of new nodes by drawing an arc through each arc in the pull-down circuit that lies between the corresponding pairs of areas.
Draw the resulting pull-up network with a pFET for each of the new arcs labeled with the same literal as on the nFET from which it came.
The justification
The complement of a Boolean expression can be obtained by taking its dual, replacing ANDs with ORs and ORs with ANDs and complementing the variables,
The graphical dual corresponds directly to the algebraic dual.
Complementation of the variables takes place automatically because each nFETs is replaced with a pFET.

23. Complex CMOS Gates Functional Design (3/3)
This method is illustrated by the generation of the pull-up from the pull-down shown.
On the dual graph, which of the two side nodes is labeled VDD or OUT is functionally arbitrary. The selection may, however, affect the location of capacitances, and hence, the performance.
OUT
OUT
VDD 1 A B A B A D
VDD
OUT D B C C D C 2
OUT
GND

24. Complex CMOS Gates Device Sizing in Complex Gates (1/4)
Method used for sizing NAND and NOR gates also applies to complex gates
Most easily transferred by examining all possible paths from OUT to GND (and from VDD to OUT)
Suppose that we are dealing with CMOS and the sized inverter devices use minimum channel lengths and widths Wn and Wp.
For the pull-down network:
Find the length nmax of the longest paths between OUT and through GND the network. Make the width of the nFETs on these paths nmaxWn In this algorithm, a path is a series of FETs that does not contain any complementary pair of literals such as X and X.
For next longest paths through the circuit between OUT and GND consisting of nFETs not yet sized, repeat Step 1.
Repeat Step 2 until there are no full paths consisting of unsized nFETS

25. Complex CMOS Gates Device Sizing in Complex Gates (2/4)
For each longest partial path in the circuit consisting of unsized nFETs, based on the longest path between OUT and GND on which it lies, find the equivalent Weq required for the partial path.
Repeat Step 1 for each longest partial path from Step 4 with OUT and GND replaced the endpoints of the partial path. Make the widths of devices on the path equal to nmaxWeq where nmax is the number of FETs on the partial path.
Repeat 4 and 5 for newly generated longest partial paths until all devices are sized.

26. Complex CMOS Gates Device Sizing in Complex Gates (3/4)B A C
OUT D
GND E F G H
This can be illustrated for the example above. Ln =0.5μ, Wn=5 μ, in the inverter.
A longest path through the network from OUT to GND is A-B-C-D with nmax=4. Thus, the widths WA, WB, WC, WD are 45=20 μ. This is the only longest path we can find from

27. Complex CMOS Gates Device Sizing in Complex Gates (4/4)
OUT to GND without passing through a sized device.
H and G are partial path. But it is important that they are considered as part of a longest between OUT and GND for evaluation. Thus, a “split” partial path consisting of H and G must be considered. Based on the evaluation segments, Weq =2Wn=10μ. Thus, WH and WG are 110=10 μ.
The longest remaining partial path in the circuit is E-F with nmax = 2. Since this path is in series with A with width 4Wn=20 μ, it needs to have an equivalent width of Weq determined from:
Weq = 20/3 μ and the widths WE and WF are 220/3 μ=40/3 μ.
Since all devices are sized, we are finished.

28. Complex CMOS Gates Layout of Complex Gates (1/4)
Goal: Given a complex CMOS logic gate, how to find a minimum-area layout.
VDD
OUT B A C D E
pMOS network
nMOS network

29. Complex CMOS Gates Layout of Complex Gates (2/4)
Arbitrary ordering of the polysilicon columns:
The separation between the polysilicon columns must allow for one diffusion-to-diffusion separation and two metal-to-diffusion contacts in between
 Consume a considerable amount of extra silicon area V DD D S S D S D
pMOS D S S D
Out D S
nMOS D S D S D S S D
GND A E B D C

30. Complex CMOS Gates Layout of Complex Gates (3/4)
Euler Path Approach
Objective: To order the inputs such that the diffusion breaks between input polysilicon strips is minimized, thereby reducing the width of the layout.
Definition: An Euler path is an uninterrupted path that traverses each gate of the graph exactly once.
Approach:
Draw the graph for the NMOS and PMOS networks.
Find a common Euler path through both of the graphs.
Note that nodes with an odd number of attached edges must be at the end points of the Euler path.
Some circuits may not have Euler paths – Do Euler paths for parts of the circuit in such cases. A circuit constructed using the dual graph method is more likely to have an Euler path.
Order the transistor pairs in the layout in the order of the path from left to right or right to left.

31. Complex CMOS Gates Layout of Complex Gates (4/4)
pMOS network A B C D E
nMOS network
Common Euler path
E-D-A-B-C
Euler path successful: Order: E-D-A-B-C
Do the symbolic layout (stick diagram)
More compact, simple routing of signals, and consequently, less parasitic capacitance
Out V DD
GND D S A
pMOS
nMOS E B C

32. Complex CMOS Gates AOI Gates
AOI (AND-OR-INVERT): Enable the sum-of-products realization of a Boolean function in one logic gate.
The pull-down network consists of parallel branches of series-connected nMOS driver transistors.
The corresponding pull-up network can be found using the dual-graph concept.
Example: OUT = A1A2A3+B1B2+C1C2C3
VDD
Dual pMOS
Pull-up network A1 A2 A3
OUT A1 B1 B1 C1 B2 A2 C2 C1 C2 C3 A3 B2 C3

33. Complex CMOS Gates OAI Gates
OAI (OR-AND-INVERT): Enable the product-of-sums realization of a Boolean function in one logic gate.
The pull-down network consists of series branches of parallel-connected nMOS driver transistors.
The corresponding pull-up network can be found using the dual-graph concept.
OUT = (A1+A2+A3)(B1+B2) C1
VDD
Dual pMOS
Pull-up network
OUT C1 B1 A3 B2 A2 A1

34. Complex CMOS Gates Pseudo-NMOS
In Pseudo-NMOS, the PMOS network is replaced by a single pFET with its gate attached to GND. This provides a fixed load such as on NMOS circuits, hence called pseudo-NMOS.
Advantage: Eliminate the PMOS network and hence reduce area.
Disadvantages:
Back to ratioed design and VOL problems as in NMOS since PFET is always ON.
“Non-zero” static power dissipation.
VDD
OUT C1 B1 A3 B2 A2
pMOS transistor
acting as load

35. Goal: To reduce the number of devices over complementary CMOS
Ratioed Logic (1/2)
Ratioless Logic: The logic levels are not dependent upon the relative device sizes.
Ratioed Logic: The logic levels are determined by the relative dimensions of composing transistors V DD SS
PDN In 1 2 3 F R L
Load
Resistive
Depletion
PMOS
Load V
< 0 T
Load V SS
PDN
(a) resistive load
(b) depletion load NMOS
(c) pseudo-NMOS
Goal: To reduce the number of devices over complementary CMOS

36. • Assymetrical response • Static power consumption
Ratioed Logic (2/2) V DD •
N transistors + Load
Resistive
• V
= V
Load OH DD R L R
• V = OL PN V DD F R
+ R PN L In 1
• Assymetrical response In
PDN 2 In
• Static power consumption 3
• t
= 0.69 R C pL L L V SS

37. Active Loads

38. Pseudo-NMOS Smaller area and load but Static power dissipation!!! V FDD F C A B C D L V = V
(similar to complementary CMOS) OH DD
Smaller area and load but Static power dissipation!!!

39. CMOS Full-Adder CircuitB
Cin S
Cout
Carry status
delete 1
propagate
generate A B
Cout
Sum
Cin
Full
adder

40. CMOS Full-Adder Circuit The Binary Adder
Cout
Sum
Cin
Full
adder
Sum = ABCin
= ABCin + ABCin + ABCin + ABCin
= ABC + (A+B+C)Cout
Cout = AB + BCin + ACin
at least two of A, B, and C are zeros

41. CMOS Full-Adder Circuit Express Sum and Carry as a Function of P, G, D
Define three new variable which ONLY depend on A, B
Generate (G) = AB
Propagate (P) = AB
Delete (D)= A B
Cout(G,P) = G+PCin
Sum(G,P) = PCin
Can also derive expressions for S and Cout based on D and P.
G = 1: Ensure that the carry bit will be generated
D = 1: Ensure that the carry bit will be deleted
P = 1: Guarantee that an incoming carry will be propagated to Cout
Note that G, P and D are only functions of A and B and are not dependent on Cin

42. CMOS Full-Adder Circuit The Ripple-Carry Adder
The N-bit adder is constructed by cascading N full-adder circuits.
The carry bit ripples from one stage to the other.
The delay through the circuit depends upon the number of logic stages which need to be traversed, and is a function of the applied signals.
Worst case delay linear with the number of bits
p = O(N)
adder  (N-1)carry + sum
Goal: Make the fastest possible carry path circuit FA A B S 1 2 3 C i ,0 o ( = ,1 ) ,2 ,3

43. CMOS Full-Adder Circuit Transistor-Level of One-Bit Full-Adder CircuitX V DD o S
28 transistors

44. CMOS Full-Adder Circuit Inversion PropertyB S C o i FA
S(A,B,Ci) = S(A,B,Ci)
Co(A,B,Ci) = Co(A,B,Ci)

45. CMOS Full-Adder Circuit Minimize Critical Path by Reducing Inverting Stages (1/2)
Even cell
Odd cell A B A B A B A B 1 1 2 2 3 3 C C C C C i ,0 o ,0 o ,1 o ,2 o ,3 FA FA FA FA S S S S 1 2 3 A B A B A B A B 1 1 2 2 3 3 C C C C C i ,0 o ,0 o ,1 o ,2 o ,3 FA FA FA FA S S S S 1 2 3

46. *FA' is a full adder without the inverter in the carry path.
CMOS Full-Adder Circuit Minimize Critical Path by Reducing Inverting Stages (2/2)
Even cell
Odd cell A B A B A B A B 1 1 2 2 3 3 C C C C C i ,0 o ,0 o ,1 o ,2 o ,3
FA'
FA'
FA'
FA' S S S S 1 2 3
*FA' is a full adder without the inverter in the carry path.
Exploit Inversion Property
The number of inverting stages in the carry path is reduced.
The only disadvantage is that it need different cells for the even and old slices.

47. CMOS Full-Adder Circuit A Better Structure: The Mirror Adder (1/3)
Carry Generation Circuitry
Carry-inverting gate is eliminated
PDN and PUN networks are not dual
D or G is high  C0 is set to VDD or GND
P is high  the incoming carry is propagated to C0
Cout(G,P) = G+PCin
Sum(G,P) = PCin V DD V DD C i A B V A DD A B B A B C B i
Kill
"0"-Propagate A C C i o S C i
"1"-Propagate
Generate A B C A i B
24 transistors

48. CMOS Full-Adder Circuit The Mirror Adder (2/3)
Only need 24 transistors.
NMOS and PMOS chains are completely symmetrical. This guarantees identical rising and falling time if the NMOS and PMOS devices are properly sized.
A maximum of two series transistors can be observed in the carry generation circuitry.
The critical issue is to minimize the capacitance at node C0.
Capacitance at node C0
4 diffusion capacitances
2 internal gate capacitances
6 gate capacitances in the connecting adder cell
 A total 12 gate capacitances (Assume Cdiffusion  Cgate)
The transistors connected to Ci are placed closest to the output.
Only the transistors in the carry stage have to be optimized for speed. All transistors in the sum gate can be minimum-size.

49. CMOS Full-Adder Circuit The Mirror Adder (3/3)Co B A A A B B A Ci V DD B A B C B A C C A B i i C i o C o S
Stick Diagram
GND

50. Pass Transistors
The pass transistor is an nFET used as a switch-like element to connect logic and storage.
Used in NMOS; sometimes used in CMOS to reduce cost.
The voltage on the gate, VC, determines whether the pass transistor is “open” or “closed” as a switch.
If VC = H, it is “closed” and connects Vout to Vin.
If VC = L, it is “open” and Vout is not connected to Vin.
Consider Vin = L and Vin = H with VC = H. With Vin = L, the pass transistor is much like a pull-down transistor in an inverter or NAND gate. So Vout, likewise, becomes L. But, for Vin = H, the output becomes the effective source of the FET. When VGS = VDD-VOUT=VTn , the nFET cuts off. The H level is VOUT = VDD-VTn.
Vin
Vout VC
VC = 1
VC = 0

51. Transmission Gates (Pass Gates) (1/2)
With body effect, for VDD = 5V, the value on Vout can be around 3.0 to 3.5 V. This reduced level diminishes NMH and the current drive for the gate or gates driven by the pass transistor.
For both NMOS and CMOS, the lack of current drive slows circuit operation and NMH can be particularly problematic. As a consequence, in CMOS, a pFET is added to form a transmission gate.
Transmission Gates
Symbols: A B C
Circuit
Popular Usage

52. Transmission Gates (2/2)
Operation
C is logic high  Both transistors are turned on and provide a low-resistance current path between nodes A and B.
C is logic low  Both transistors will be off, and the path between nodes A and B will be open circuit. This condition is called the high-impedance state.
With the parallel pFET added, it can transfer a full VDD from A to B (or B to A). It can also charge driven capacitance faster.
The substrates of NMOS and PMOS are connected to ground and VDD, respectively. Therefore, the substrate-bias effect must be taken into account.

53. Transmission Gates DC Analysis (1/3)
Vin = VDD, VC = VDD, and node B is connected to a capacitor, which represents capacitive loading of the subsequent logic stages.
The nMOS transistor, VDS,n=VDD–Vout, and VGS,n=VDD–Vout. Thus,
Turn off: If Vout > VDD – VT,n
Saturation: If Vout < VDD – VT,n
The pMOS transistor, VDS,p=Vout–VDD, and VGS,p= –VDD. Thus,
Saturation: If Vout < |VT,p |
Linear: If Vout > |VT,p |
Vin=VDD
Vout 0V
VDD
ISD,p
IDS,n ID

54. Transmission Gates DC Analysis (2/3)
nMOS: saturation
pMOS: saturation
pMOS: linear reg.
nMOS: cut-off
Region 1
Region 2
Region 3 0V
|VT,p|
(VDD-VT,n )
VDD
Vout
The current flowing through the transmission gate is equal to
ID = IDS,n + ISD,p
The equivalent resistance for each transistor can be represented as
Req,n = (VDD-Vout)/IDS,n
Req,p = (VDD-Vout)/ IDS,p
and
Req = Req,n ║ Req,p

55. Transmission Gates DC Analysis (3/3)
The values of Req,n and Req,p
Region 1
Region 2
Region 3

56. Resistance of Transmission Gate
Req,n
Req,p
VDD-VT,n
VDD
Vout R
Req,n║ Req,p
The parallel combination of the pFET and the nFET result in an equivalent resistance that is roughly constant. This constant value, Req, can be used in series with an ideal switch controlled by C and C to model the transmission gate. See p. 311 of the text book.
The implementation of CMOS transmission gates in logic circuit design usually results in compact circuit structures which may even require a smaller number of transistors.

57. Applications of Transmission Gate Example: XORB F M1 M2
M3/M4 AB AB
Only need 6 transistors

58. Applications of Transmission Gate Example: MultiplexerB S
F = AS+BS BS AS

59. Similar delays for sum and carry
Applications of Transmission Gate Examples: Transmission Gate Full Adder
Generate (G) = AB
Propagate (P) = AB
Cout(G,P) = G+PCin
Sum(G,P) = PCin P
VDD
VDD Ci A P S
Sum Generation A A P Ci A P
VDD B B A
VDD P P Co
Carry Generation Ci Ci Ci A P
Setup
Similar delays for sum and carry