1. False Path

2. Timing analysis problems We want to determine the true critical paths of a circuit in order to: –To determine the minimum cycle time that the circuit will function –To identify critical paths for performance optimization – don’t want to try to optimize the wrong (non-critical) paths Implications: –Don’t want false paths (produced by static delay analysis)

3. False paths Static analysis is fast but leads to false paths Path of length 400 is never “exercised” Approaches: –Mark orthogonal pairs –(may be wrong, can’t find all possibilities, is the method correct?) Throw out “non-sensitizable” (false) paths Circuit delay = Length of longest path ? –Not a good enough bound (too pessimistic) Circuit delay = Time of last output change This leads to functional timing analysis for false paths 200 100 200 100 MUX 0101 s v fifi y 0101 u x

4. First attempt: Boolean difference Intuition: Check for “static false path”: Path P = {f 0, f 1, f 2, …, f n } gives conditions under which node fi is “sensitive” to node fi- 1 So output of P is sensitive to f 0 if Recall Boolean difference: Example: f i-1 fifi F i+1

5. Example: Static false path and Hence, Thus (by previous condition) any path is not “statically sensitizable” and is “false” 200 100 200 100 MUX 0101 s u v fifi x y 0101

6. Definitions Given a simple gate (i.e. AND, OR, NAND, NOR), a controlling value on an input determines the output of the gate independent of the other inputs Given a simple gate (i.e. AND, OR, NAND, NOR), a non-controlling value on an input cannot determine the output of the gate independent of the other inputs Example: 0 is a controlling value for AND gate. 1 is non-controlling value for AND gate Note: Controlling / non-controlling value is merely a specialization of the Boolean difference to simple gates abab abab f g

7. Static sensitization Simple Gates: Let path P = {f 0, f 1, …, f i } A side-input to a gate f i along P is any input other than f i-1 An event is a transition from 0 to 1 or 1 to 0 Path P is statically sensitizable if there exists a primary input vector under which every side-input is set to a non-controlling value A path is a “statically false path” if it is not statically sensitizable (see previous example)

8. Static sensitization and false paths Static sensitization is wrong! Paths shown in bold are not statically sensitizable, but delay of circuit is 3 a b d c e f g abcdefgabcdefg t= 0 1 2 3

9. Why static sensitization fails Static sensitization falls because it considers only the final value on each side-input. It does not consider values on side-inputs at the moment the event propagates from f i-1 through node f i For example, in previous circuit when determining static sensitization of path {b, e, f, g} we assume side-input a of gate e is at final non-controlling value of 1. This is not necessary for the path to be sensitizable

10. Dynamic Sensitizable Path Given a path P = s 0 -g 0 -s 1 -……g k -s k in a circuit C. Path P is a dynamic sensitizable path if and only if there is at least one input vector such that for all signals s i, (1) s i is the earliest controlling input of gate g i (2) s i is he latest non-controlling input of gate g i and the side inputs of gate g i are non- controlling inputs.

11. Early-arrive-signals (s i, *) = {s j | s j is an input signal gate g i and Max-arrive-time(s j ) < MinPD(s i, P, *)} Late-arrrive-signals (s i, *) = {s j | s j is an input signal gate g i and Min-arrive-time (s j ) > MaxPD (s i, P, *)} Algorithm false_path_checking (P, false_path) let P be the path to be checked and P=s 0, g 0, s 1, g 1, …,s i, g i, …, s k Where s 0 and s k are a primary input and a primary output respectively let Q be the event Queue and the format of event is (s i, val), Where val is the logic value assigned to signal s i begin {The event generating phase} Initialize Q for each s i alogn the path P do begin for each s j  Early-arrive-signals(s i, *) do begin enqueue(s j, val = non-control value of gate g i ) into Q end if Late-arrive-signals(s i, *)  then begin enqueue(s i, val=control value of gate g i ) into Q end