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Processor implementation on Altera DE2 Development and Education Board

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Presentation on theme: "Processor implementation on Altera DE2 Development and Education Board"— Presentation transcript:

1 Processor implementation on Altera DE2 Development and Education Board
V. Mitić, M. Petković, D. Todorović 1, Volker Zerbe 2 1 - University of Nis, Faculty of Electronic Engineering; University of Applied Sciences, Erfurt

2 Agenda Introducing to: Hardware Software
Altera Developement and Education Boards FPGAs Software Programming tools for FPGAs VHDL

3 Introduction Technology Altera Quartus II
DE2 Development and Education Board

4 DE2 Development and Education Board

5 Elements of the board used
Role Switches SW10 TO SW18 NUMBER A Switches SW0 TO SW7 NUMBER B Swithes SW8 and SW9 OPERATION SELECTOR Pushbuttons KEY0 TO KEY 3 OPERATION SELECTOR, TRIGGER LEDs LEDR0 TO REDL8 RESULT (in binary numeral system) Displays HEX0 TO HEX2 RESULT (in decimal numeral system)

6 Design, fabrication and code
Processor Block Diagram/Schematic file Operations symbols 8bitadder, 8bitsupstract, 8bitand, 8bitor, 8bitnot, 8bitxor, 8bitnand, 8bitnor Multiplexer symbols Multiplexernot, Multiplexer, Multiplexer2, Multiplexerrez HEXdec symbol Converter symbol

7 Input selector switches
HEXdec Input numbers Operations Multiplexers Output Displays Input pushbuttons Output LEDs Input selector switches Processor Block Diagram/Schematic file

8 Operations symbols Symbol name Role Number of I/O pins 8bitadder
Addition of two numbers 8/9 8bitsupstract Substraction of two numbers 8bitand Logical AND 8/8 8bitor Logical OR 8bitnot Logical NOT 8bitxor Logical XOR 8bitnand Logical NAND 8bitnor Logical NOR

9 Operations symbols 8bitadder Addition is done with the use of two symbols: halfadder and fullader. Symbol name Input pins Output pins HALFADDER A,B SUM,CARRY FULLADDER A,B,CARRY_IN

10 HALFADDER FULLADDER

11 Number of selector pins
Multiplexer symbols Symbol name Number of input pins Number of output pins Number of selector pins Multiplexernot 16 8 2 Multiplexer 34 9 4 Multiplexer2 32 Multiplexerrez 17

12 Multiplexernot There are two 8-bit numbers on the input and two selector pins (SEL0-SEL1) There is one 8-bit number on the output. The output number is eaqual to one of the input numbers depending of the selector pins.

13 HEXdec symbol This symbol performs conversion of a binary number, which is at the input, into a decimal number which is displayed on the 7- segment displays. There are 9 input and 49 output pins. The conversion from binary to decimal numeral system is implemented using converter symbol. Representation of a number onto 7-segment display is done with symbols HEX0-HEX9.

14 Converter symbol This symbol is a graphical representation of converter.vhd file that is written in VHDL code. This symbol does not only convert the number, but also it “determines” the distribution of digits in the decimal number. There are 9 input pins and 29 output pins. All commands are executed in a process (named CONVERSION) because they have to be executed sequentially (one by one).

15 Results in brief Aquired knowlage about:
Elements and posibilities of DE2 Development and Education Board Basics of VHDL (via converter.vhd) Altera Quartus tools for synthesis and simulation FPGAs

16 Conclusion DE2 Developement and Education board advantages
FPGA advantages VHDL advantages Implementation: from lab demos to ESA projects

17 Thank you for your attention!
Any questions?

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