1. The versatile hardware accelerator framework for sparse vector calculations Michał Karwatowski 1,2, Kazimierz Wiatr 12 1 AGH University of Science and Technology, al. Mickiewicza 30, 30-059 Kraków, 2 ACK Cyfronet AGH, ul. Nawojki 11, 30-950 Kraków RUC 17-18.09.2015 Kraków

2. Agenda Text processing Sparse data Hardware architecture Results Future work 2

3. Text similarity analysis 3

4. Sparse data 4 V0 0001 0011 0100 0110 1001 1100 1111 V1 0000 0010 0011 0111 1010 1100 V2 0010 0110 1001 1100 V3 0001 0010 0011 0100 0110 0111 1001 1010 1011 1110 V4 0011 0100 0101 0111 1001 V5 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 V6 0001 0011 0101 1001 1100 1111 V7 0010 0011 0100 1000 1100 1101 1110 1111

5. Text comparison 5

6. Top level hardware architecture 6

7. Hardware processing system 7

8. Cascaded stream splitter 8

9. Processing channel 9

10. ZedBoard Dual-core ARM Cortex-A9 667 MHz 512 MB RAM connected to PS FPGA XC7Z020 85k logic cells 140 block RAMs 10

11. VC707 Intel Core i7 950 3066 MHz 12 GB RAM FPGA XC7VX485T 485k logic cells 1030 block RAMs PCIe Gen2x8 11

12. Resource utilization – 8 channels 12

13. Power usage 13

14. Work in progress 32 internal channels in Zynq 192 internal channels in Virtex Database in DDR3 memory OpenCL 14

15. Questions 15