1. Partizionamento HW/SW nell'implementazione di sistemi real-time su FPGA con softcore

2. Outline Intro & Motivation Model Algorithms Experiments

3. Intro and Motivation Past work on design optimization for single- processor scheduling –Realizing that the schedulability condition can be viewed as a feasibility region in the domain of the design variables –Realizing that such region is convex for EDF under reasonable assumptions Availability of Softcores for FPGAs –NIOS II for Altera Co-design problem –a functionality can be implemented in HW (inside the FPGA) in SW (inside or outside the FPGA) and executed by one or more (How many?) Softcores.

4. Motivation Start from some system Model (Simulink) Explore different HW design options (0-1-2-4- … NIOS) For each design option find optimal design configuration by means of convex linear optimization HW implementation is subject to area constraints SW implementation is subject to schedulability constraints

5. HW (area) Constraints Models available: Single-dimension Condition linear bound slottedlinear

6. HW (area) Constraints Models available: –2-dimensions cutting stock problem Complex, more realistic and extremely well- studied problem (real-world implications) linear bound solutions can be found from operations research literature !

7. Reality of FPGAs (additional resource constr.)

8. Schedulability constraints EDF (or L&L sufficient) bound How realistic is it? Implementations of FP and EDF on NIOS exist How about deadline=periods, independence and so on?

9. The Model Starting point: Simulink model

10. The Model implementation of a Simulink model HW implementation: market tools exist (Celoxica) for implementing Simulink blocks in FPGA.

11. The Model SW implementation: market tools exist RT- Workshop+embedded coder (Mathworks) or TergetLink (Dspace) for implementing Simulink blocks as a set of concurrent threads. Threads inherit the sampling period of the blocks (periodic model) No overrun is permitted (deadlines=periods) Communication is by switched buffers (asynchronous, tasks are independent) Of course code generation and switched buffers are not commercially available for EDF but there is nothing that prevents their implementation

12. The Model FPGA = rectangular area of Logic Elements (Les). All dimensions will be in terms of Les FPGA height = H FPGA width = W Assume homogeneous bidimensional model of FPGA (array of Les) k Softcores CPU l l=1..k are implemented in FPGA: each core requires an area slsh (k=0, 1, 2..) H W sh sw

13. The Model System model = network of blocks V = {F 1, F 2, … F n } is the set of functional block A block F i can be implemented in HW or SW. according to the value of s il  {0,1}. s il =1 if block F i is executed in SW upon CPU l. If not executed in SW a block MUST be implemented in HW. If implemented in HW, a block requires an area w i  h i If implemented in SW, a block F i has a worst case comp. time  i and a period of execution t i. (HW implementation has  i  0) u i =  i /t i

14. The Model If implemented in SW, a block is executed in the context of a thread with the same period. m i,j =1 if F i is mapped for execution in  j and 0 otherwise (these are not optimization variables but constants!) Schedulability constraint (for each NIOS)

15. Results to be exploited Cutting Stock approximate (linear) solution: Level packing (Lodi) pack the items in row forming levels –the first level is the bottom of the bin, the second level is built on top of the first and so on … In each level, the leftmost item is the tallest one The bottom level is the tallest one Items are sorted and renunmbered by non- increasing h i values.

16. Results to be exploited An example: there are n potential levels (one for each initializing block)

17. Results to be exploited Variables: y i = 1 if item i initializes level i and 0 otherwise Objective (original): –minimize the height of the required rectangle

18. Results to be exploited Constraints (original): –x ij, i {1.. n-1}, j>i, x ij =1 if item j is packed in level i, 0 otherwise Each item is packed exactly once Width constraint

19. Reusing Results These results can be reused as follows: The original objective can be retained or it can become a constraint

20. Results to be exploited The existence of a packing (Each item is packed exactly once) Becomes … Each item is packed exactly once or it is executed on a CPU

21. Results to be exploited The width constraint is retained … A schedulability constraint must be added for eack CPU Options: Minimize height with the utilization constraint Minimize utilization with height constraint

22. Problem The available area is not squared! The area necessary for implementing the k CPUs must be considered Solution: start with the 1-CPU case: there are two possible partitionings H W sh sw H-sh W-sw Duplicate all packing variables (the complexity of the problem is correspondingly increased)

23. Problem For the k-CPU case additional assumptions are required (CPUs are packed by rows, columns, or …) H W sh sw H - k sh W - k sw H W H - 2 sh W - 2 sw

24. Experimenting with GPLK Demo …