1. DBBC - EVN CDR Meeting, Bologna May 2005 DBBC Project G. Tuccari, S. Buttaccio, G. Nicotra - Istituto di Radioastronomia CNR, Sezione di Noto - Italy M. Wunderlich - Max Planck Institute fuer Radioastronomie, Bonn - Germany Y. Xiang - Shanghai Astronomical Observatory, CAS – China G. Balodis - Faculty of Electronics and Telecommunications, University of Riga - Latvia

2. DBBC - EVN CDR Meeting, Bologna May 2005 DBBC Project overview The main goal is to replace the existing terminal with a complete compact system to be used with any VSI compliant recorder or data transport Hardware programmability is the main feature in order to optimize the architecture to the needed performance having the possibility to arrange different architecture in the same hardware support Maximum Input and Output data rates are the limitation and are set so to satisfy the present and near future necessities The new development is compatible with the existing terminals and correlators

3. DBBC - EVN CDR Meeting, Bologna May 2005 DBBC Project overview (cont.) The new set of BBCs is fully up-gradable and ready to process in a future larger bandwidth with modified correlators Upgrade or improvements will be mostly only software Upgrade is also possible in hardware replacing compatible ‘pin- to-pin’ processing modules Data out as VSI interface and modified MK4 formatter

4. DBBC - EVN CDR Meeting, Bologna May 2005 DBBC General Features Four IF Input in the range 1-512, 512-1024, 1024-1536, 1536-2048 MHz Four polarizations or bands available for a single group of output data channel selection 2 30 =1.073.741.824 Hz frequency sampling clock Channel bandwidth ranging between 250KHz to 32 MHz Tuning step 1 Hz or less if required Station based fringe counter-rotation possible Multiple architecture using fully re-configurable FPGA Core Modules Modular realization for cascaded processing

5. DBBC - EVN CDR Meeting, Bologna May 2005 DBBC General Schematic View A/D 1 cPCI Linux PC FS PC 1074 MHz Synthesizer Distributor H-Maser MK4/VSI max 64 ch CORE HSI HSO cPCI Interfaces IFn (MHz) 1~512, 512~1024, 1024~1536, 1536~2048 AGC/ Filter IF 4IF 3IF 2IF 1 A/D 2 A/D 1 A/D 2 HSIR HSOR CORE HSI HSO HSIR HSOR AGC/ Filter AGC/ Filter AGC/ Filter CORE HSI HSO HSIR HSORCollector D/A Monitor

6. DBBC - EVN CDR Meeting, Bologna May 2005 Schematic Top View 6U x 84 TE x 360 mm A/D min 1- max 4 (4 for a VLBA equivalent system) CoreModule min 1 – max 16 (8 for a VLBA equivalent system) VSI MK4 Analog IF1 IF2 IF3IF4 10 MHz 1 PPS Fs IF1 IF2 IF3 IF4 cPCI Linux PC and Interfaces FiLa Ethernet DISKDISK 1 PPS Fs/2 Fs/4 JTAG 1.5V Vcore 3.3V Dig 3.3V VAux 3.3V An 1.5V Vcore 5V12V

7. DBBC - EVN CDR Meeting, Bologna May 2005 System Components Analog to digital converter ‘environment’ 1074 MHz Synthesizer (commercial) CoreModule boards FPGAs Core Firmware Configurations DA monitor FiLa board (data insertion and collector) VSI interface PCI interfaces (commercial) Linux PC Board (commercial) System Management Software + Field System Integration

8. DBBC - EVN CDR Meeting, Bologna May 2005 Analog to digital converter ‘environment’ Conversion Clock Fs=1.073.741.824 Hz or Fs/2, Fs/4, Fs/8 MAX108 AD converter (under evaluation ATMEL AT84AS003) Front-end power level control Bandwidth 1-512 / 512-1024 / 1024-1536 / 1536-2048 MHz selection/filtering Total power measurement LVPECL differential data bus (ATMEL: LVDS)

9. DBBC - EVN CDR Meeting, Bologna May 2005 A/D Board Schematic View AD CONVERTER RX IF 2X8bit Data LVPECL differential Power Level Control Anti-image Analog Filter Total Power Interface 1PPS H-Maser 1074 MHz Synthesizer Band Reduction

10. DBBC - EVN CDR Meeting, Bologna May 2005 AD Board Layout

11. DBBC - EVN CDR Meeting, Bologna May 2005 DBBC CoreModule A single module able to process more channels More modules can be arranged in cascade External buses: HIS/HSIR, HSO/HSOR, CCM/CCMR HSI Input data bus, is propagated with HSIR HSO Output data bus, is shared for multiple IF access CCM/R Control/Configuration/Monitor bus

12. DBBC - EVN CDR Meeting, Bologna May 2005 DBBC Core Modules Cascade Architecture HSI | HSIR CORE HSO CORE HSOR HSOHSORHSO HSOR CORE HSO HSOR Stream IF 1-2-3-4 To Collector and VSI interface HSI | HSIR

13. DBBC - EVN CDR Meeting, Bologna May 2005 DBBC CORE Module Features Different configuration can be supported: SSB down converter Wide band parallel FIR Polyphase FIR + FFT A module able to handle: Maximum Input bandwidth 8.192 Gbit/s Maximum Output bandwidth 4.096 Gbit/s Control/Configuration bus through a common PCI interface

14. DBBC - EVN CDR Meeting, Bologna May 2005 Core Module Board HIS/HSIR Cascade-able Input Bus 4x2x8bit @512 MHz equivalent HSO Shared Output bus 2x32bit @32, 64MHz CCM Control / Configuration bus 32bit CCM Monitor bus to DA converter 12 bit @32,64 MHz 1 FPGA VirII-1152pin, 3000 - 4000 - 6000 – 8000 (to be evaluated Xilinx V4 device) ‘Sandwich’ cascade method

15. DBBC - EVN CDR Meeting, Bologna May 2005 CoreModule Layout

16. DBBC - EVN CDR Meeting, Bologna May 2005 Digital Down Converter Configuration SSB conversion between high data rate sampled IF band and lower data rate base band LO as a Numerically Controlled Oscillator Mixer as Complex as Look Up Table multiplier Low-pass band filter Finite Impulse Response (FIR) filters cascade Decimation because of the high ratio between IF and output data rate performed with CIC or multirate/multistage FIR Bandwidth: 16, 8, 4, 2, 1, 0.5, 0.25 MHz

17. DBBC - EVN CDR Meeting, Bologna May 2005 Linux PC Board: System Management Software Standard commercial PC board including HD Configuration files for each FPGA stored on HD Software interface for FPGA configuration Software interface for servicing FPGAs (I/O registers access) Software interface for A/D level control

18. DBBC - EVN CDR Meeting, Bologna May 2005 Software Management Structure Field System PC cPCI PC + INT FPGA Module FPGA Module FPGA Module HD Etherne t AD

19. DBBC - EVN CDR Meeting, Bologna May 2005 DBBC Prototype Status at April 2005 AD Environment: - Conditioning modules developed (IRA) - AD Board developed, to be realized (MPI) CoreModule: - Board developed, to be realized (IRA) - FPGA firmware configurations (IRA+SHAO): –0.5, 1, 2, 4 MHz bwd, completed, –0.25, 8, 16 MHz bwd, near to completion, to be tested –0.125, 0.0625, 0.03125, 32 MHz ready in simulation –tunable base band with 1 Hz resolution –tuning range in Nyquist blocks of 64 and 128 MHz ready –tuning range in Nyquist blocks of 256, 512 MHz ready in simulation, under development

20. DBBC - EVN CDR Meeting, Bologna May 2005 DBBC Prototype Status at April 2005 (cont) Insertion/Collector board: developed, to be realized (IRA) Monitor: to be realized (IRA) Synthesizer: commercial + ad hoc: developed, to be realized 1.5V high current power supply ready (IRA) cPCI under Linux PC: commercial cPCI interfaces: commercial Communication software: partially done (SHAO)

21. DBBC - EVN CDR Meeting, Bologna May 2005 DBBC Prototype Performance (Apr 2005) Preliminary testing has been done in laboratory for the developed configurations Good performance in conversion and tuning have been measured from 0 up to 2.5 GHz Today with appropriate Nyquist zone pre-selection, L and S band can be directly down-converted and recorded with modified MK4 formatter (Noto and Seshan) Testing with real observation started with mDBBC (IRA- SHAO agreement): fringes detected in analog-digital and digital-digital baselines.

22. DBBC - EVN CDR Meeting, Bologna May 2005 First Results with the mDBBC prototype (collaboration Italy-China) First digital x analog fringes detected on Nov 23, 2004 in the Seshan-Urumuqi baseline First digital x digital fringes detected on Feb 2, 2005 in the Noto-Seshan baseline

23. DBBC - EVN CDR Meeting, Bologna May 2005 Conclusions The DBBC system is an high flexible instrument because is able to produce independent tunable channels for a full compatibility with the existing acquisition system and correlators. One CoreModule board is replacing a BBC module. The DBBC system is able to handle polyphase + FFT architectures for producing contiguous not tunable channels. One CoreModule board is able to produce multiple channels. Both solutions are possible within the same system adopting a variable number of AD and CoreModule units