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MOBY DIC TOOLBOX MOBY DIC TOOLBOX MOBY-DIC WORKSHOP Noordwijkerhout, 23-08-2012 MOBY-DIC WORKSHOP Noordwijkerhout, 23-08-2012.

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Presentation on theme: "MOBY DIC TOOLBOX MOBY DIC TOOLBOX MOBY-DIC WORKSHOP Noordwijkerhout, 23-08-2012 MOBY-DIC WORKSHOP Noordwijkerhout, 23-08-2012."— Presentation transcript:

1 MOBY DIC TOOLBOX MOBY DIC TOOLBOX MOBY-DIC WORKSHOP Noordwijkerhout, 23-08-2012 MOBY-DIC WORKSHOP Noordwijkerhout, 23-08-2012

2 DESCRIPTION C / C++ compiler Object oriented programming HTML Documentation Multi Parametric Toolbox (MPT) MATLAB R2008a or newer Requirements: Hybrid Toolbox Main features: Graphical User Interface MATLAB / SIMULINK GPL v2 license (open source) http://ncas.dibe.unige.it/software/MOBY-DIC_Toolbox/ Yalmip MATLAB R2011a and Xilinx System Generator (only for HDL simulation)

3 CONTROL/CIRCUIT CO-DESIGN PLANT EMBEDDED CONTROLLER EMBEDDED CONTROLLER Fast Small Low-power Low-cost Fast Small Low-power Low-cost

4 GOAL OF THE TOOLBOX (1) Control/circuit co-design CONTROL SPECS. CIRCUIT SPECS. LINEAR SYSTEM CONSTRAINTS DIGITAL CIRCUIT FPGA/ASIC IMPLEMENTATION CLOSED-LOOP SIMULATION

5 CONTROL DESIGN @linearSystem object LINEAR SYSTEM CONSTRAINTS @constraints object CONTROL SPECS. GENERATE MPC PWAG generateMPC function Calls Hybrid Toolbox or Multi Parametric Toolbox to compute explicit MPC control law generateMPC function Calls Hybrid Toolbox or Multi Parametric Toolbox to compute explicit MPC control law @pwag object Piecewise Affine function defined over generic polytopic partition @pwag object Piecewise Affine function defined over generic polytopic partition

6 CIRCUIT DESIGN synthesize method Generates VHDL files for the circuit implementation of exact MPC controller. More solutions are available, the choice is performed based on circuit specifications synthesize method Generates VHDL files for the circuit implementation of exact MPC controller. More solutions are available, the choice is performed based on circuit specifications CIRCUIT SPECS. synthesize VHDL files getCircuitPerformances PWAG Latency, multipliers, memory occup. getCircuitPerformances Gets information about circuit performances in advance. getCircuitPerformances Gets information about circuit performances in advance.

7 CONTROL APPROXIMATION pwasApproximation Approximates the PWAG controller with a Piece-Wise Affine function defined over a simplicial partition, by imposing constraints. pwasApproximation Approximates the PWAG controller with a Piece-Wise Affine function defined over a simplicial partition, by imposing constraints. LINEAR SYSTEM CONSTRAINTS APPROXIMATE PWAS / PWAR PWAG pwarApproximation Approximates the PWAG controller with a Piece-Wise Affine function defined over a rectangular partition, by imposing constraints. pwarApproximation Approximates the PWAG controller with a Piece-Wise Affine function defined over a rectangular partition, by imposing constraints.

8 APPROXIMATION BENEFITS Regularity of the partition Fast circuit computation Stability can be proven (a posteriori) PWAG/PWAS/ PWAR PWAG/PWAS/ PWAR STABILITY TEST

9 CIRCUIT DESIGN synthesize method Generates VHDL files for the circuit implementation of approximate MPC controller. synthesize method Generates VHDL files for the circuit implementation of approximate MPC controller. CIRCUIT SPECS. synthesize VHDL files getCircuitPerformances PWAS/PWAR Latency, multipliers, memory occup. getCircuitPerformances Gets information about circuit performances in advance, also before generating the approximate control function itself. getCircuitPerformances Gets information about circuit performances in advance, also before generating the approximate control function itself.

10 CLOSED-LOOP SIMULATION generateSimulinkModel Generates a Simulink model of the closed-loop system, in which the control is computed by simulating the VHDL files (delays and fixed point representation effects are taken into account) Requires Xilinx System Generator generateSimulinkModel Generates a Simulink model of the closed-loop system, in which the control is computed by simulating the VHDL files (delays and fixed point representation effects are taken into account) Requires Xilinx System Generator VHDL files PLANT PWAG / PWAS / PWAR GENERATE SIMULINK MODEL

11 VIRTUAL SENSOR DESIGN PLANT Inputs u Unmeasurable output z Measurable outputs y VIRTUAL SENSOR Estimated unmeasurable output z Estimated unmeasurable output z Fast Small Low-power Low-cost Fast Small Low-power Low-cost

12 VIRTUAL SENSOR THEORY

13 GOAL OF THE TOOLBOX (2) Virtual sensors design SENSOR SPECS. CIRCUIT SPECS. DATASET DIGITAL CIRCUIT FPGA/ASIC IMPLEMENTATION VALIDATION

14 VIRTUAL SENSOR DESIGN identify Identify a PWAS virtual sensor starting from measures of u, y and z identify Identify a PWAS virtual sensor starting from measures of u, y and z TRAINING DATASET SENSOR SPECS. IDENTIFY VIRTUAL SENSOR The estimation of z is performed by computing the value of a PWAS function of u, y and the estimated z at previous time instants

15 VIRTUAL SENSOR VALIDATION validate Validates the virtual sensor on a test set to see if the estimation is accurate validate Validates the virtual sensor on a test set to see if the estimation is accurate TEST DATASET VALIDATE VIRTUAL SENSOR

16 VIRTUAL SENSOR CIRCUIT VIRTUAL SENSOR CIRCUIT SPECS. VHDL files synthesize synthesize method Generates VHDL files for the circuit implementation of PWAS virtual sensor. More solutions are available, the choice is performed based on circuit specifications synthesize method Generates VHDL files for the circuit implementation of PWAS virtual sensor. More solutions are available, the choice is performed based on circuit specifications


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