1. © Digital Integrated Circuits 2nd Memories Digital Integrated Circuits A Design Perspective SemiconductorMemories Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic December 20, 2002

2. © Digital Integrated Circuits 2nd Memories Chapter Overview  Memory Classification  Memory Architectures  The Memory Core  Periphery  Reliability  Case Studies

3. © Digital Integrated Circuits 2nd Memories Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory EPROM E 2 PROM FLASH Random Access Non-Random Access SRAM DRAM Mask-Programmed Programmable (PROM) FIFO Shift Register CAM LIFO

4. © Digital Integrated Circuits 2nd Memories Memory Architecture: Decoders Word 0 Word 1 Word 2 WordN 2 2 N 2 1 Storage cell M bitsM N words S 0 S 1 S 2 S N 2 2 A 0 A 1 A K 2 1 K 5 log 2 N S N 2 1 Word 0 Word 1 Word 2 WordN 2 2 N 2 1 Storage cell S 0 Input-Output (M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals K = log 2 N Decoder reduces the number of select signals Input-Output (M bits) Decoder

5. © Digital Integrated Circuits 2nd Memories Block Diagram of 4 Mbit SRAM Subglobal row decoder Global row decoder Subglobal row decoder Block 30 Block 31 128 K Array Block 0 Block 1 Local row decoder [Hirose90]

6. © Digital Integrated Circuits 2nd Memories Read-Only Memory Cells WL BL WL BL 1 WL BL WL BL WL BL 0 V DD WL BL GND Diode ROMMOS ROM 1MOS ROM 2

7. © Digital Integrated Circuits 2nd Memories MOS OR ROM WL[0] V DD BL[0] WL[1] WL[2] WL[3] V bias BL[1] Pull-down loads BL[2]BL[3] V DD

8. © Digital Integrated Circuits 2nd Memories MOS NOR ROM WL[0] GND BL[0] WL[1] WL[2] WL[3] V DD BL[1] Pull-up devices BL[2]BL[3] GND

9. © Digital Integrated Circuits 2nd Memories MOS NOR ROM Layout Programmming using the Active Layer Only Polysilicon Metal1 Diffusion Metal1 on Diffusion Cell (9.5 x 7 )

10. © Digital Integrated Circuits 2nd Memories MOS NOR ROM Layout Polysilicon Metal1 Diffusion Metal1 on Diffusion Cell (11 x 7 ) Programmming using the Contact Layer Only

11. © Digital Integrated Circuits 2nd Memories MOS NAND ROM All word lines high by default with exception of selected row WL[0] WL[1] WL[2] WL[3] V DD Pull-up devices BL[3]BL[2]BL[1]BL[0]

12. © Digital Integrated Circuits 2nd Memories MOS NAND ROM Layout No contact to VDD or GND necessary; Loss in performance compared to NOR ROM drastically reduced cell size Polysilicon Diffusion Metal1 on Diffusion Cell (8 x 7 ) Programmming using the Metal-1 Layer Only

13. © Digital Integrated Circuits 2nd Memories NAND ROM Layout Cell (5 x 6 ) Polysilicon Threshold-altering implant Metal1 on Diffusion Programmming using Implants Only

14. © Digital Integrated Circuits 2nd Memories Equivalent Transient Model for MOS NOR ROM  Word line parasitics  Wire capacitance and gate capacitance  Wire resistance (polysilicon)  Bit line parasitics  Resistance not dominant (metal)  Drain and Gate-Drain capacitance Model for NOR ROM V DD C bit r word c WL BL

15. © Digital Integrated Circuits 2nd Memories Equivalent Transient Model for MOS NAND ROM  Word line parasitics  Similar to NOR ROM  Bit line parasitics  Resistance of cascaded transistors dominates  Drain/Source and complete gate capacitance Model for NAND ROM V DD C L r word c c bit r WL BL

16. © Digital Integrated Circuits 2nd Memories Decreasing Word Line Delay

17. © Digital Integrated Circuits 2nd Memories Precharged MOS NOR ROM PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design. WL[0] GND BL[0] WL[1] WL[2] WL[3] V DD BL[1] Precharge devices BL[2]BL[3] GND pre f

18. © Digital Integrated Circuits 2nd Memories Non-Volatile Memories The Floating-gate transistor (FAMOS) Floating gate Source Substrate Gate Drain n + n +_ p t ox t Device cross-section Schematic symbol G S D

19. © Digital Integrated Circuits 2nd Memories Floating-Gate Transistor Programming 0 V 2 5 V 0 V DS Removing programming voltage leaves charge trapped 5 V 2 2.5 V 5 V DS Programming results in higherV T. 20 V 10 V5 V 20 V DS Avalanche injection

20. © Digital Integrated Circuits 2nd Memories FLOTOX EEPROM Floating gate Source Substrate p Gate Drain n 1 n 1 FLOTOX transistor Fowler-Nordheim I-V characteristic 20–30 nm 10 nm -10 V 10 V I V GD

21. © Digital Integrated Circuits 2nd Memories EEPROM Cell WL BL V DD Absolute threshold control is hard Unprogrammed transistor might be depletion  2 transistor cell

22. © Digital Integrated Circuits 2nd Memories Flash EEPROM Control gate erasure p-substrate Floating gate Thin tunneling oxide n 1 source n 1 drain programming Many other options …

23. © Digital Integrated Circuits 2nd Memories Cross-sections of NVM cells EPROMFlash Courtesy Intel

24. © Digital Integrated Circuits 2nd Memories NAND Flash Memory Word linesSelect transistor Bit line contactSource line contact Active area STI Courtesy Toshiba

25. © Digital Integrated Circuits 2nd Memories Characteristics of State-of-the-art NVM

26. © Digital Integrated Circuits 2nd Memories Read-Write Memories (RAM)  STATIC (SRAM)  DYNAMIC (DRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended

27. © Digital Integrated Circuits 2nd Memories 6-transistor CMOS SRAM Cell WL BL V DD M 5 M 6 M 4 M 1 M 2 M 3 BL Q Q

28. © Digital Integrated Circuits 2nd Memories CMOS SRAM Analysis (Read) WL BL V DD M 5 M 6 M 4 M 1 V V V BL Q = 1 Q = 0 C bit C

29. © Digital Integrated Circuits 2nd Memories CMOS SRAM Analysis (Read) 0 0 0.2 0.4 0.6 0.8 1 1.2 0.5 Voltage rise [V] 11.21.52 Cell Ratio (CR) 2.53 Voltage Rise (V)

30. © Digital Integrated Circuits 2nd Memories CMOS SRAM Analysis (Write) BL = 1 = 0 Q = 0 Q = 1 M 1 M 4 M 5 M 6 V DD V WL

31. © Digital Integrated Circuits 2nd Memories CMOS SRAM Analysis (Write)

32. © Digital Integrated Circuits 2nd Memories 6T-SRAM — Layout V DD GND Q Q WL BL M1 M3 M4M2 M5M6

33. © Digital Integrated Circuits 2nd Memories Resistance-load SRAM Cell Static power dissipation -- Want R L large Bit lines precharged to V DD to address t p problem M 3 R L R L V DD WL QQ M 1 M 2 M 4 BL

34. © Digital Integrated Circuits 2nd Memories SRAM Characteristics

35. © Digital Integrated Circuits 2nd Memories 3-Transistor DRAM Cell No constraints on device ratios Reads are non-destructive Value stored at node X when writing a “1” = V WWL -V Tn WWL BL1 M 1 X M 3 M 2 C S 2 RWL V DD V 2 V T D V V 2 V T BL2 1 X RWL WWL

36. © Digital Integrated Circuits 2nd Memories 3T-DRAM — Layout BL2BL1GND RWL WWL M3 M2 M1

37. © Digital Integrated Circuits 2nd Memories Sense Amp Operation D V(1) V V(0) t V PRE V BL Sense amp activated Word line activated

38. © Digital Integrated Circuits 2nd Memories 1-T DRAM Cell Uses Polysilicon-Diffusion Capacitance Expensive in Area M 1 word line Diffused bit line Polysilicon gate Polysilicon plate Capacitor Cross-section Layout Metal word line Poly SiO 2 Field Oxide n + n + Inversion layer induced by plate bias Poly

39. © Digital Integrated Circuits 2nd Memories SEM of poly-diffusion capacitor 1T-DRAM

40. © Digital Integrated Circuits 2nd Memories Advanced 1T DRAM Cells Cell Plate Si Capacitor Insulator Storage Node Poly 2nd Field Oxide Refilling Poly Si Substrate Trench Cell Stacked-capacitor Cell Capacitor dielectric layer Cell plate Word line Insulating Layer IsolationTransfer gate Storage electrode

41. © Digital Integrated Circuits 2nd Memories Static CAM Memory Cell

42. © Digital Integrated Circuits 2nd Memories CAM in Cache Memory Address Decoder Hit Logic CAM ARRAY Input Drivers TagHit Address SRAM ARRAY Sense Amps / Input Drivers DataR/W

43. © Digital Integrated Circuits 2nd Memories Periphery  Decoders  Sense Amplifiers  Input/Output Buffers  Control / Timing Circuitry

44. © Digital Integrated Circuits 2nd Memories Row Decoders Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder

45. © Digital Integrated Circuits 2nd Memories Hierarchical Decoders A 2 A 2 A 2 A 3 WL 0 A 2 A 3 A 2 A 3 A 2 A 3 A 3 A 3 A 0 A 0 A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 1 A 1 1 Multi-stage implementation improves performance NAND decoder using 2-input pre-decoders

46. © Digital Integrated Circuits 2nd Memories Dynamic Decoders Precharge devices V DD  GND WL 3 2 1 0 A 0 A 0 GND A 1 A 1  WL 3 A 0 A 0 A 1 A 1 2 1 0 V DD V V V 2-input NOR decoder 2-input NAND decoder

47. © Digital Integrated Circuits 2nd Memories 4-input pass-transistor based column decoder Advantages: speed (t pd does not add to overall memory access time) Only one extra transistor in signal path Disadvantage: Large transistor count 2-input NOR decoder A 0 S 0 BL 0 1 2 3 A 1 S 1 S 2 S 3 D

48. © Digital Integrated Circuits 2nd Memories 4-to-1 tree based column decoder Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders buffers progressive sizing combination of tree and pass transistor approaches Solutions: BL 0 1 2 3 D A 0 A 0 A 1 A 1

49. © Digital Integrated Circuits 2nd Memories Decoder for circular shift-register

50. © Digital Integrated Circuits 2nd Memories Sense Amplifiers t p C  V  I av ----------------= make  V as small as possible smalllarge Idea: Use Sense Amplifer output input s.a. small transition

51. © Digital Integrated Circuits 2nd Memories Differential Sense Amplifier Directly applicable to SRAMs M 4 M 1 M 5 M 3 M 2 V DD bit SE Out y

52. © Digital Integrated Circuits 2nd Memories Latch-Based Sense Amplifier (DRAM) Initialized in its meta-stable point with EQ Once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point. EQ V DD BL SE

53. © Digital Integrated Circuits 2nd Memories Charge-Redistribution Amplifier― EPROM SE V DD WLC Load Cascode device Column decoder EPROM array BL WL V casc Out C out C col C BL M 1 M 2 M 3 M 4

54. © Digital Integrated Circuits 2nd Memories Open bitline architecture with dummy cells C S C S C S C S BLL LL 1 L 0 R 0 C S R 1 C S L … … BLR V DD SE EQ Dummy cell

55. © Digital Integrated Circuits 2nd Memories DRAM Read Process with Dummy Cell 3 2 1 0 0123 V BL t (ns) reading 0 3 2 1 0 0123 V SE EQWL t (ns) control signals 3 2 1 0 0123 V BL t (ns) reading 1

56. © Digital Integrated Circuits 2nd Memories Voltage Regulator - + V DD V REF V bias M drive M V DL V V REF Equivalent Model

57. © Digital Integrated Circuits 2nd Memories DRAM Timing

58. © Digital Integrated Circuits 2nd Memories RDRAM Architecture memory array mux/demux network Data bus Clocks Column Row demux packet dec. Bus k k 3 l demux

59. © Digital Integrated Circuits 2nd Memories Address Transition Detection DELAY t d A 0 t d A 1 t d A N 2 1 V DD ATD …

60. © Digital Integrated Circuits 2nd Memories Reliability and Yield

61. © Digital Integrated Circuits 2nd Memories Sensing Parameters in DRAM From [Itoh01] 4K 10 100 1000 64K1M16M256M4G64G Memory Capacity (bits/chip) C D, Q S, C S, V DD, V smax C D(1F) C S Q S(1C) V smax(mv) V DD(V) Q S 5 C S V DD /2 V smax 5 Q S /(C S 1 C D )

62. © Digital Integrated Circuits 2nd Memories Noise Sources in 1T DRam C cross electrode a -particles leakage C S WL BL substrate Adjacent BL C WBL

63. © Digital Integrated Circuits 2nd Memories Open Bit-line Architecture —Cross Coupling Sense Amplifier C WL 1 BL C C WBL C CC WL 0 C C BL CC WL D D 0 1 BL EQ

64. © Digital Integrated Circuits 2nd Memories Alpha-particles (or Neutrons) 1 Particle ~ 1 Million Carriers WL BL V DD n 1 a -particle SiO 2 1 1 1 1 1 1 2 2 2 2 2 2

65. © Digital Integrated Circuits 2nd Memories Yield Yield curves at different stages of process maturity (from [Veendrick92])

66. © Digital Integrated Circuits 2nd Memories Redundancy Memory Array Column Decoder Row Decoder Redundant rows Redundant columns Row Address Column Address Fuse Bank :

67. © Digital Integrated Circuits 2nd Memories Error-Correcting Codes Example: Hamming Codes with e.g. B3 Wrong 1 1 0 = 3

68. © Digital Integrated Circuits 2nd Memories Redundancy and Error Correction

69. © Digital Integrated Circuits 2nd Memories Sources of Power Dissipation in Memories PERIPHERY ROW DEC selected non-selected CHIP COLUMN DEC nC DE V INT f mC DE V INT f C PT V INT f I DCP ARRAY m n m(n 2 1)i hld mi act V DD V SS I DD 5S C i D V i f 1S I DCP From [Itoh00]

70. © Digital Integrated Circuits 2nd Memories Data Retention in SRAM (A) SRAM leakage increases with technology scaling

71. © Digital Integrated Circuits 2nd Memories Suppressing Leakage in SRAM SRAM cell SRAM cell SRAM cell V DD,int V DD V V DDL V SS,int sleep SRAM cell SRAM cell SRAM cell V DD,int sleep low-threshold transistor Reducing the supply voltage Inserting Extra Resistance

72. © Digital Integrated Circuits 2nd Memories Case Studies  Programmable Logic Array  SRAM  Flash Memory

73. © Digital Integrated Circuits 2nd Memories PLA versus ROM  Programmable Logic Array structured approach to random logic “two level logic implementation” NOR-NOR (product of sums) NAND-NAND (sum of products) IDENTICAL TO ROM!  Main difference ROM: fully populated PLA: one element per minterm Note: Importance of PLA’s has drastically reduced 1.slow 2.better software techniques (mutli-level logic synthesis) But …

74. © Digital Integrated Circuits 2nd Memories Programmable Logic Array GND V DD V X 0 X 0 X 1 f 0 f 1 X 1 X 2 X 2 AND-planeOR-plane Pseudo-NMOS PLA

75. © Digital Integrated Circuits 2nd Memories Dynamic PLA GND V DD V X 0 X 0 X 1 f 0 f 1 X 1 X 2 X 2 AND f f OR f f AND-planeOR-plane

76. © Digital Integrated Circuits 2nd Memories Clock Signal Generation for self-timed dynamic PLA f t pre t eval f AND f f f f OR f (a) Clock signals(b) Timing generation circuitry Dummy AND row

77. © Digital Integrated Circuits 2nd Memories PLA Layout

78. © Digital Integrated Circuits 2nd Memories Bit-line Circuitry Bit-line load Block select ATD BEQ LocalWL Memory cell I/O line I/O B/T CD Sense amplifier CD I/O B/T

79. © Digital Integrated Circuits 2nd Memories Sense Amplifier (and Waveforms) BS I/OI/O DATA Block selectATD BSSA BS SEQ De i I/O Lines Address Data-cut ATD BEQ SEQ DATA Vdd GND SA, SA Vdd GND

80. © Digital Integrated Circuits 2nd Memories 125mm 2 1Gbit NAND Flash Memory 10.7mm 11.7mm 2kB Page buffer & cacheCharge pump 16896 bit lines 32 word lines x 1024 blocks From [Nakamura02]

81. © Digital Integrated Circuits 2nd Memories 125mm 2 1Gbit NAND Flash Memory  Technology 0.13  m p-sub CMOS triple-well 1poly, 1polycide, 1W, 2Al  Cell size 0.077  m2  Chip size 125.2mm2  Organization 2112 x 8b x 64 page x 1k block  Power supply 2.7V-3.6V  Cycle time 50ns  Read time 25  s  Program time 200  s / page  Erase time 2ms / block  Technology 0.13  m p-sub CMOS triple-well 1poly, 1polycide, 1W, 2Al  Cell size 0.077  m2  Chip size 125.2mm2  Organization 2112 x 8b x 64 page x 1k block  Power supply 2.7V-3.6V  Cycle time 50ns  Read time 25  s  Program time 200  s / page  Erase time 2ms / block From [Nakamura02]

82. © Digital Integrated Circuits 2nd Memories Semiconductor Memory Trends (up to the 90’s) Memory Size as a function of time: x 4 every three years

83. © Digital Integrated Circuits 2nd Memories Semiconductor Memory Trends (updated) From [Itoh01]

84. © Digital Integrated Circuits 2nd Memories Trends in Memory Cell Area From [Itoh01]

85. © Digital Integrated Circuits 2nd Memories Semiconductor Memory Trends Technology feature size for different SRAM generations