1. 2010 IEEE ICECS - Athens, Greece, 12-15 December1 Using Flash memories as SIMO channels for extending the lifetime of Solid-State Drives Maria Varsamou and Theodore Antonakopoulos Department of Electrical and Computers Engineering, University of Patras, Greece e-mail: mtvars@upatras.gr, antonako@upatras.gr website: www.loe.ee.upatras.grmtvars@upatras.gr,antonako@upatras.gr www.loe.ee.upatras.gr 17th International Conference on Electronics, Circuits, and Systems

2. 2010 IEEE ICECS - Athens, Greece, 12-15 December2 Presentation Outline  Introduction  Solid-State Drives  Flash memory technology  Solid-State Drives lifetime  Experiment for NAND flash characterization  Method for extending the flash endurance  Experimental results  Conclusions

3. 2010 IEEE ICECS - Athens, Greece, 12-15 December3 Solid-State Drives (SSDs)  SSDs have become a mature solution for consumer and enterprise applications  SSDs have to demonstrate similar or better performance compared to magnetic disks  SSDs performance metrics:  Data reliability (retention and endurance)  I/O performance (kIOPs and latency)  SSDs use Flash memories (SLC/MLC)  SSDs performance depends on:  Used Flash technology  Supported workload  Internal architecture  High-level functions  Flash memory demonstrates a time-varying behavior in terms of raw BER and wears out as workload (P/E cycles) increases DRAM memory Flash Channel #1 FCC Flash Die Flash Die Flash Channel #M FCC Flash Die Flash Die Main Processor DRAM memory Host Interface DMA engines

4. 2010 IEEE ICECS - Athens, Greece, 12-15 December4 V T is shifted by injecting electrons into the floating gate; V T is shifted back by removing the electrons. Control gate Floating gate Bulk Flash memory cell Vcc R i cell array cell V cell V cg Ids Vcg “1” “0” Erased “1” Programmed “0” Vt – Programming = Electrons stored on the FG = High Vt – Erasing = Remove electrons from the FG = Low Vt – Threshold Voltage shift =  Q FG /C CG Floating gate isolated in oxide

5. 2010 IEEE ICECS - Athens, Greece, 12-15 December5 Retention: capability of keeping the stored information in time. Endurance: capability of maintaining the stored information after erase, program and read cycling. High voltages are applied during block erase (all pages of a block) page program (all cells of a page and adjacent pages) And a high electric field is applied to the tunnel oxide and that results to oxide aging. Flash memory error conditions More frequent error conditions Variations on the stored charge(more permanent errors) Variations on the detected voltage during read (more temporary errors) Shift in operating margin (more permanent errors) Probability 1  0 is much higher than the probability 0  1 1  0 typical error condition during the life-time of a flash cell 0  1 error condition only at the end of the life-time of a flash cell

6. 2010 IEEE ICECS - Athens, Greece, 12-15 December6 Typical NAND IC Architecture  A number of NAND Flash cells forms a page  A number of pages forms a block  Read/Write per page  Erase per block  Overwriting is not permitted NAND Interfaces  ONFI 1.0 Asynchronous 40 Mbytes/sec  ONFI 2.0 Synchronous 166/200 Mbytes/sec

7. 2010 IEEE ICECS - Athens, Greece, 12-15 December7 NAND Read/Write Page Write Page Read

8. 2010 IEEE ICECS - Athens, Greece, 12-15 December8 Type Std SLCMLCEnterprise MLC Consumer MLC Interface ONFI2.0 Capacity per NAND Die (Gbits)16 32 Page size (bytes)4K+224 Pages per block128 256 Page Read (usecs)2550 Page Write (usecs)2007001600900 Block Erase (usecs)700200040003000 max Sustained READ Data Rate (MBps) 8053 max Sustained WRITE Data Rate (MBps) 1852.54.4 Endurance (Pr/Er cycles)100K10K30K5K NAND Flash memory

9. 2010 IEEE ICECS - Athens, Greece, 12-15 December9 Experimental Setup for Flash Characterization Ethernet Host Computer JTAG USB ML507 Flash board Main Memory PPC44 0 Etherne t Virtex5 FPGA KernelONFI 2.0 Flash Interface Ethernet TCP/IP Flash Memory Chips MATLAB

10. 2010 IEEE ICECS - Athens, Greece, 12-15 December10 Raw BER of SLC Flash memory Block Best Page Worst Page Bit Error Ratio (BER)

11. 2010 IEEE ICECS - Athens, Greece, 12-15 December11 Raw BER of MLC Flash memory

12. 2010 IEEE ICECS - Athens, Greece, 12-15 December12 Methods for extending the Lifetime of SSDs  Error Correction Codes (BCH, RS, LDPC etc., additional parity information)  Wear-leveling (System level, intra-block)  Exploit the characteristics of the error insertion mechanism (proposed method) S: user space E: endurance (number of P/E cycles) V: user written space per time unit A: write amplification

13. 2010 IEEE ICECS - Athens, Greece, 12-15 December13 SLC Endurance Measurements  Page Size: 4320 bytes  Experiment: Erase block, Write all pages with random data, Read all pages, Compare Target user BER: 10 -15 1 0 1 0 Tx Rx SLC Channel Model

14. 2010 IEEE ICECS - Athens, Greece, 12-15 December14 Extending the endurance nWnW + + Write nRnR + + Read #1 Read #N nRnR nRnR  BCH (n, k) code: error correction capability of t-error bits  BCH error correction capability can be extended to 2t using erasures  The errors can be:  Write and Read related  Permanent and Temporary  The SLC channel inserts errors that only change the bits from ‘1’ to ‘0’  We read the corrupted page additional times and estimate erasures according to bit differences SISO SIMO

15. 2010 IEEE ICECS - Athens, Greece, 12-15 December15 Proposed Correction Method Hardware complexity  The correction mechanism is activated only when the user data can not be recovered.  In this case, a small delay is introduced, comparable with the delay introduced during BCH decoding.

16. 2010 IEEE ICECS - Athens, Greece, 12-15 December16 Performance of the proposed method As the number of read cycles increases, the method's performance also improves, but with less gain.

17. 2010 IEEE ICECS - Athens, Greece, 12-15 December17 Effect on Flash Controller I/O Performance DRAM memory Flash Channel #1 FCC Flash Die Flash Die Flash Channel #M FCC Flash Die Flash Die Main Processor DRAM memory Host Interface DMA engines Flash Controller Architecture  Today’s high performance SSDs support:  Large number of Flash channels, usually 16  A few Gbytes of SLC memory are used per channel  Host interface data rate of a few Gbps  Expected I/O Rate for 16 channels:  ~ 300 KIOPs, no pipeline  ~ 600 KIOPs, with pipeline  Measured I/O Rate: ~ 120 KIOPs  Limited by:  Internal architecture  Latency introduced by ECC  Flash related functions (wear leveling, garbage collection, etc.) The proposed method for extending flash endurance does not decrease the SSD’s storage efficiency (no additional parity) and does not affect the I/O performance as long as the used ECC can correct all errors.

18. 2010 IEEE ICECS - Athens, Greece, 12-15 December18 Conclusions  The lifetime of an SSD can be extended by improving the endurance of its Flash memories  A method that exploits the error characteristics of SLC Flash memory to identify possible error locations was proposed:  Sustains the memory endurance for a few tens of thousands P/E cycles  Limited hardware complexity  No additional parity bits are required (N o decrease the SSD’s storage efficiency ).  Does not affect the SSD’s I/O performance during normal operation and as long as the used ECC scheme can recover any corrupted data.