1. 1 Wire Length Prediction-based Technology Mapping and Fanout Optimization Qinghua Liu Malgorzata Marek-Sadowska VLSI Design Automation Lab UC-Santa Barbara

2. 2 Outline  Motivation and previous work  Pre-layout wire length prediction  Technology mapping with wire-length prediction  Fanout optimization with wire-length prediction  Experimental results  Conclusions and future work

3. 3 Motivation  Traditional logic synthesis does not consider accurate layout information  Placement quality depends on netlist structure placement algorithm

4. 4 Previous work  Logic and physical co-synthesis Layout-driven logic synthesis Local netlist transformations Metric-driven structural logic synthesis  Adhesion  Distance

5. 5 Pre-layout wire-length prediction  Previous work Statistical wire-length prediction  Lou Sheffer et al. “Why Interconnect Prediction Doesn’t work?” SLIP’00 Individual wire-length prediction  Qinghua Liu et al. “Wire Length Prediction in Constraint Driven Placement” SLIP’03  Semi-individual wire-length prediction Predict that nets have a tendency to be long or short  Qinghua Liu et al. “Pre-layout Wire Length and Congestion Estimation” DAC’04

6. 6 Summary of the semi-individual wire length prediction technique  Predict lengths of connections Mutual contraction  Predict lengths of multi-pin nets by Net range

7. 7 Mutual contraction B.Hu and M.Marek-Sadowska, “Wire length prediction based clustering and its application in placement” DAC’03 u v x y

8. 8 Relative weight of a connection u v x y W r (x, y) = 0.5 W r (u, v) = 0.71 EQ1 EQ2

9. 9 EQ3 C p (x, y) = Wr(x, y) Wr(y, x) x y j W r (x, y) = 0.71 W r (y, x) = 0.6 C p (x, y) = 0.426 u v i W r (u, v) = 0.71 W r (v, u) = 0.33 C p (u, v) = 0.234 Mutual contraction of a connection

10. 10 Predictions on connections (a) (b) Mutual contraction vs. Connection length

11. 11 Net range 0 1 2 3 4 5 6 7 8 9 10 11 Example of net range Circuit depth

12. 12 Net range vs. average length for multi-pin nets Predictions on multi-pin nets

13. 13 Technology mapping with wire- length prediction (WP-Map)  Node Decomposition  Technology Mapping

14. 14 G a b c a b c a b c Node decomposition T.Kutzschebauch and L.Stok, “Congestion aware layout driven logic synthesis”, ICCAD’01

15. 15 CurrentPinNum= CurrentPinNum-1 CurrentPinNum=n Decompose(G,n 1,n 2 ) Remove n 1 and n 2, insert new net Y Done N Decompose n-input gate G with wire length prediction CurrentPinNum>2? (n 1,n 2 )=two input nets with largest mutual contraction Update mutual contraction Greedy node decomposition algorithm

16. 16 Correlation between mutual contraction and interconnection complexity Average mutual contraction vs. Rent’s exponent

17. 17 Technology mapping EQ4

18. 18 Fanout optimization with wire- length prediction (WP-Fanout)  Net selection Select all large-degree nets Select small-degree nets with large net range  Net decomposition Circuit depth LT-treeBalanced tree

19. 19 Experiment setting  LGSyn93 benchmark suite Optimized by script.rugged Mapped with 0.13um industrial standard cell library  Placement is done by mPL4  Global routing is done by Labyrinth

20. 20 Experimental results  Compare with the traditional area-driven technology mapping algorithm implemented in SIS  Results of the WP-Map algorithm  Results of combined WP-Map and WP- Fanout algorithm

21. 21 Compare WP-Map with SIS Compare mapped netlists

22. 22 Compare WP-Map with SIS (cont.) Average cut number distribution of C6288

23. 23 Compare WP-Map with SIS (cont.) Results after placement and global routing

24. 24 Compare WP-Map + WP-Fanout with SIS Results after placement and global routing

25. 25 Conclusions  Wire length can be predicted in structural level Mutual contraction Net range  Wire length prediction technique can be applied into technology mapping and fanout optimization 8.7% improvement on average congestion 17.2% improvement on peak congestion

26. 26 Future work  Logic extraction with wire-length and congestion prediction  Timing-driven technology mapping with wire-length prediction