1. BaBar Silicon Vertex Tracker Status and Prospects Adam Cunha UC Santa Barbara for the BaBar SVT Group 7 November 2005 Vertex2005, Nikko, Japan adamcun@slac.stanford.edu

2. Adam Cunha 2 Outline Overview of BaBar Overview of Silicon Vertex Tracker (SVT) Recent SVT issues and solutions Pedestal shift Leakage current increase in outer layers Impact of possible chip loss SVT performance projections Conclusion

3. Adam Cunha 3 Reconstruct CP state Determine time between decays from vertices Boosted Υ(4S) l- K-K- J/ψ KSKS µ+µ+ µ-µ- e-e- e+e+ B0B0 B0B0 Δz=(βγc)Δt π+π+ π-π- slow pion The BaBar Experiment Scientific Objective Study CP violation in B meson decays. Over-constrain CKM quark mixing matrix. SVT Performance Requirements Δz resolution < 130 µm (average Δz for B 0 decays = 280µm). Single vertex resolution < 80 µm. Stand-alone tracking for p T < 100 MeV/c with 80-90% efficiency.

4. Adam Cunha 4 Cherenkov Detector (DIRC) 144 quartz bars K, separation Electromagnetic Calorimeter 6580 CsI crystals e + ID,   and reco Drift Chamber 40 layers Tracking + dE/dx Instrumented Flux Return 19 layers of RPCs (LSTs)   and K L ID Silicon Vertex Tracker 5 layers of double sided silicon strips e + [3.1 GeV] e - [9 GeV] The BaBar Detector SLAC: PEPII Collider

5. Adam Cunha 5  5 Layers of double-sided, AC-coupled silicon  0.94 m 2 of Si  Φ and z strips  Inner 3: Precision Vertexing  Outer 2: Pattern recognition, Low P t tracking  Custom rad-hard readout IC (the AToM chip).  Low-mass design (Kevlar/carbon fiber mechanical support) Be Beam Pipe Magnet The BaBar SVT

6. Adam Cunha 6 z-side φ-side Si wafers upilex fanout Layer 1Layer 2Layer 3Layer 4Layer 5Total min radius3.2 cm4.0 cm5.4 cm12.4 cm14.0 cm modules666161852 Si wafers6x4=24 6x6=3616x7=11218x8=144340 readout pitch (φ) 50 µm55 µm 100 µm readout pitch (Z) 100 µm 210 µm readout chips1441922402562881120 channels1843224576307203276836864~140k SVT Modules

7. Adam Cunha 7 HDI Readout Board AToM Chip A Time over Threshold Machine Time Over Threshold Readout 128 Channels per chip Simultaneous Acquisition Digitization Read-out Internal charge injection for calibration AToM Chips Upilex Fanout Mounting Buttons Berg Connector 5.7 mm 8.3 mm HDI Board AToM Chip

8. Adam Cunha 8 CAL DAC Shaper Thresh DAC Comp PRE AMP TOT Counter Time Stamp Event Time Event Number Revolving Buffer 193 Bins Si Buffer Chan # Sparsification Readout Buffer C INJ C AC Serial Data Out 15 MHz Digitization pipeline of single channel Inside the AToM Chip

9. Adam Cunha 9 Specifications Reverse-biased (50V) Si PIN diodes. Active area 1cm x 1cm x 300µm 2 rings (FWD/BWD) of 6 diodes Near Layer-1 SVT electronics Cross-section view of SVT Details DC coupled readout monitors total (leakage + radiation) current Large leakage current subtraction with temperature corrections (thermistors) Trigger beam dump when acute/chronic dose rate exceeds maximum + 2 CVD Diamonds (new) Purpose Monitor accumulated dose Protect against too high dose rates: Acute damage threshold: 1 krad/ms Chronic (10min) threshold: 50 mrad/s Radiation Monitoring (SVTRAD)

10. Adam Cunha 10 SVT Performance and Bugeted Radiation Damage

11. Adam Cunha 11 SVT Performance Average hit efficiency 97% Slow pion efficiency 70% for P T >50 MeV Average zed hit resolution 10 - 40 μm (Track-angle dependent) No radiation-induced change in performance observed so far. Phi side z side Z Resolution (μm) Adam Cunha Efficiency

12. Adam Cunha 12 Expected Damage to Electronics Gain decrease ~ 4%/Mrad Noise increase ~ 16%/Mrad G.C., A.Perazzo No digital failure observed up to 5 MRads Radiation tests were performed on the AToM chip in 2001 using 60 Co sources at SLAC and using 60 Co sources at LBL. (Also tests at Elettra, mentioned later) In the real system, the gain decreases by ~5%/Mrad, noise increases by 15-20%/Mrad Exactly the same numbers we found with the 60 Co 1 Mrad 4 Mrad Dose (Mrad)

13. Adam Cunha 13 S/N Limit of 10  Radiation budget: 5 Mrad Signal to Noise Projections

14. Adam Cunha 14 Unexpected Phenomenon

15. Adam Cunha 15 HDI Card in horizontal plane Threshold offset (counts) Channel Unexpected Phenomenon: Pedestal Shift Noise pedestal (Threshold offset) started to increase Behavior associated with AToM chip location, not with strip location Why problem? One pedestal setting per AToM chip Chip 4 20 threshold DACs = 1fC Pedestal

16. Adam Cunha 16 Pedestal Shift (cont.) Sets in at an integrated radiation dose of 1 Mrad Correlated with most irradiated channel (note highly non-uniform: peaked sharply in the horizontal plane). Effect reproduced at Elettra (test beam at Trieste, Italy) Effect reproduced @ Elettra Channel Delta Threshold (counts) narrow e - beam AToM Chip Pedestal recovers Threshold offset (counts) Integrated Radiation 1 Mrad 2 Mrad Groups of 8 channels

17. Adam Cunha 17 Pedestal Shift (cont.) Cause: Uneven radiation above 1 Mrad leads to asymmetry in AToM chip electronics Solution: Adjust threshold by chip is successful Layer 2 Module 4 10% inefficiency level Make threshold adjustment… Layer 2 Module 4 …recover efficiency.

18. Adam Cunha 18 Unexpected Phenomenon 2

19. Adam Cunha 19 Unexpected Phenomenon: Leakage Current Increase Since May 2004 an anomalous increase in the bias current for some modules has been observed Only Layer-4 modules: not a simple radiation damage effect No geometrical correlation Consequences: increasing occupancies 300uA 10uA AprMayJun I Leak (  A) Days in 2004

20. Adam Cunha 20 Leakage Current Increase No beams Decrease in leakage current Beams play a role in leakage current increase

21. Adam Cunha 21 Leakage Current Increase If we vary the reference potential of the metal strips (see next slide) it leads to a decrease in the leakage current “Phenomenon is reference-voltage dependent” Leakage Current More humidity helps to stop the effect “Humidity plays a role” Leakage Current 0 1 2 Time (hrs) Jan 24 Jan 25 Time

22. Adam Cunha 22 I Leak (  A) Time (hrs) Leakage Current Increase -20V +20V E Nside Pside Nside Psid e DV L5-L4 =+40V Hypothesis: Accumulation of static charge on the silicon surface. The charge is beam-induced drifts because of the field between the facing sides of different layers. By varying the potential drop across the air between the layers we can control the effect 1800 0000 0600 1200

23. Adam Cunha 23 Leakage Current Increase Static charge on passivated surface Charge accumulation causes an increase in the electric field at junction edge, inducing a soft junction breakdown. Charge accumulation due to trickle injection  SVT bias always on.

24. Adam Cunha 24 Leakage Current Increase Using humid air and a new reference voltage setting, the situation now is under control 180 μA 100 μA 1 June 05 - 1 July 05 Increased Humidity Leakage Current

25. Adam Cunha 25 SVT Status & Future Prospects

26. Adam Cunha 26 short Both noisy 2 chips masked short Current SVT Status Faulty AToM Chips Forward Backward 95% of detector is fully functional: 6 out of 208 readout sections not working 300 p-stop shorts/pinholes (mainly from before 2001) 2% unbonded or otherwise dead channels Redundancy proven to be sufficient

27. Adam Cunha 27 Radiation Dose History & Future Dose Projections: Midplane modules will reach 5 Mrad budget in 2008 Top & Bottom modules will reach 1 Mrad in 2006 – pedestal shift Pedestal Shift Bottom Modules Radiation Budget Midplane Modules `00 `02 `04 `06 `08 Date `00 `02 `04 `06 `08

28. Adam Cunha 28 Impact of Losing Chips on Physics 35.3% 34.5% B  J/  s 56% 51% However, no loss of Δz precision! Scenarios with up to all mid-plane L1- 2 modules OFF: (UNREALISTIC) Set E = 2 midplane chips OFF in L1& 2 (1/9 of L1/2 readout) Soft  Efficiency (%)

29. Adam Cunha 29 SVT has been successfully operated in BaBar since 1999 Effects of radiation damage Pedestal shift effect solved using bimonthly threshold optimization Electronics noise/gain degradation limits detector lifetime Rapid leakage current increase was alarming, but has been mostly reversed Adjustable reference voltages implemented Increased humidity levels also help charge dissipation Physics performance only slightly reduced in any realistic damage scenario. Conclusions

30. Adam Cunha 30 The End

31. Adam Cunha 31 Extra Slides

32. Adam Cunha 32 HDI Matching Card Kapton Tail Front Cables Si Wafers HDI Link DAQ Link Power Supplies MUX Power Back Cables Fiber Optic to DAQ Inside detector Schematic of Signal Readout  HDI: High Density Interconnect. Mounting fixture and cooling for readout ICs.  Kapton Tail: Flexible multi-layer circuit. Power, clock, commands, and data.  Matching Card: Connects dissimilar cables. Impedance matching (passive).  HDI Link: Reference signals to HDI digital common.  DAQ Link: Multiplex control, demultiplex data. Electrical -- optical conversion.

33. Adam Cunha 33 Pedestal Shift Onset

34. Adam Cunha 34 Trickle Injection Fill & Coast; Ramp down SVT during each injection Trickle Injection! (began March 2004) SVT biased all the time Lumi LER HER

35. Adam Cunha 35 Occupancy Projections Note: Electronics noise (e.g. AToM pedestal level) NOT included Predicted from background studies at various beam currents & luminosities.