1. June 18, 2001Systems Architecture II1 Systems Architecture II Systems Architecture I Review * Jeremy R. Johnson June 18, 2001 * Most figures from Computer Organization and Design: The Hardware/Software Approach, Second Edition, by David Patterson and John Hennessy, are copyrighted material (COPYRIGHT 1998 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED).

2. June 18, 2001Systems Architecture II2 A Random Access Machine Control Unit AC Program 123456... Memory AC = accumulator register

3. June 18, 2001Systems Architecture II3 Instruction Set LDA X; Load the AC with the contents of memory address X LDI X; Load the AC indirectly with the contents of address X STA X; Store the contents of the AC at memory address X STI X; Store the contents of the AC indirectly at address X ADD X; Add the contents of address X to the contents of the AC SUB X; Subtract the contents of address X from the AC JMP X; Jump to the instruction labeled X JMZ X; Jump to the instruction labeled X if the AC contains 0 JMN X; Jump to the instruction labeled X if the contents of the AC ; is negative HLT ; Halt execution

4. June 18, 2001Systems Architecture II4 Sample RAM Program 1. LDI 3; get i-th entry from A 2. ADD 4; add offset to compute index j 3. STA 5; store index j 4. LDI 5; get j-th entry from B 5. JMZ 9; if entry 0, go to 9 6. LDA 3; if entry 1, get index i 7. STA 2; and store it at 2. 8. HLT ; stop execution 9. LDA 1; get constant 1 10. STI 5; and store it in B 11. LDA 3; get index i 12. SUB 4; subtract limit 13. JMZ 8; if i = limit, stop 14. LDA 3; get index i again 15. ADD 1; increment I 16. STA 3; store new value of I 17. JMP 1; AC 1 Memory 1 constant 2 0answer 3 6Index i 4 9 Limit of A 5 0Index j 6 3 789 4 2 2 A 10111213 0 0 0 0 B

5. June 18, 2001Systems Architecture II5 MBR MAR AC ALU PC IR(C) IR(O) Memory MUX 0 1 2 3 MUX 0101 0101 01230123 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 q 9 q 8 q 7 q 6 q 5 q 4 q 3 q 2 q 1 q 0 x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 x1x2x3x4x5x1x2x3x4x5 DecoderT s s s s LOAD LOAD AD READ/ WRITE INC CLEAR INC

6. June 18, 2001Systems Architecture II6 Building Blocks

7. June 18, 2001Systems Architecture II7 Implementing Logic Gates with Transistors output gate +V ground A Transistor NOT Gate A NAND B A +V ground A Transistor NAND Gate B

8. June 18, 2001Systems Architecture II8 A Clocked Flip-Flop Q Q’ S R clock

9. June 18, 2001Systems Architecture II9 Memory Cell R Q S Q’ input read/write select output

10. June 18, 2001Systems Architecture II10 Memory

11. June 18, 2001Systems Architecture II11 MIPS Architecture Load/Store architecture General purpose register machine (32 registers) ALU operations have 3 register operands (2 source + 1 dest) 16 bit constants for immediate mode Simple instruction set –simple branch operations (beq, bne) –Use register to set condition (e.g. slt) –operations such as move built, li, blt from existing operations Uniform encoding –All instructions are 32-bits long –Opcode is always in the high-order 6 bits –3 types of instruction formats –register fields in the same place for all formats

12. June 18, 2001Systems Architecture II12 Design Principles Simplicity favors regularity –uniform instruction length –all ALU operations have 3 register operands –register addresses in the same location for all instruction formats Smaller is faster –register architecture –small number of registers Good design demands good compromises –fixed length instructions and only 16 bit constants –several instruction formats but consistent length Make common cases fast –immediate addressing –16 bit constants –only beq and bne

13. June 18, 2001Systems Architecture II13 MIPS Encoding All instructions are 32-bits long Opcode is always in the high-order 6 bits Only three instruction formats 32 registers implies 5 bit register addresses: –$zero R0 ; zero register always equal to 0 –$at R1 ; temporary register –$v0 - $v1 R2-R3 ; return registers –$a0 - $a3 R4-R7 ; argument registers –$t0 - $t7 R8-R15 ; temporary - not preserved across calls –$s0 - $s7 R16-R23 ; saved registers - preserved across calls –$t8 - $t9 R24-R25 ; temporary not preserved across calls –$k0 - $k1 R26-R27 ; reserved by OS kernel –$gp R28 ; global pointer –$sp R29 ; stack pointer –$fp R30 ; frame pointer –$ra R31 ; return address

14. June 18, 2001Systems Architecture II14 MIPS Instruction Set Arithmetic/Logical –add, sub, and, or –addi, andi, ori Data Transfer –lw, lb –sw, sb –lui Control –beq, bne –slt, slti –j, jal, jr

15. June 18, 2001Systems Architecture II15 MIPS Instruction Formats R format (register format - add, sub, …) I format (immediate format - lw, sw, …) J format (jump format – j, jal) op rs rt rd shamt func op rs rt address op 26-bit constant

16. June 18, 2001Systems Architecture II16 MIPS Addressing Modes Immediate Addressing –16 bit constant from low order bits of instruction –addi $t0, $s0, 4 Register Addressing –add $t0, $s0, $s1 Base Addressing (displacement addressing) –16-bit constant from low order bits of instruction plus base register –lw $t0, 16($sp) PC-Relative Addressing –(PC+4) + 16-bit address (word) from instruction –bne $s0, $s1, Target Pseudodirect Addressing –high order 4 bits of PC+4 concatenated with 26 bit word address - low order 26 bits from instruction shifted 2 bits to the left –j Address

17. June 18, 2001Systems Architecture II17 MIPS Memory Convention

18. June 18, 2001Systems Architecture II18 sub $sp,$sp,8 # push stack sw $ra,4($sp) # save return address sw $a0,0($sp) # save n slt $t0,$a0,1 # test n < 1 beq $t0,$zero,L1 # branch if n >= 1 add $v0,$zero,1 # return 1 add $sp,$sp,8 # pop stack jr $ra # return to calling procedure L1: sub $a0,$a0,1 # set parameter to n-1 jal fact # call fact(n-1) lw $a0,0($sp) # restore previous value of n lw $ra,4($sp) # restore previous return address mul $v0,$a0,$v0 # return n * fact(n-1) add $sp,$sp,8 # pop stack jr $ra # return to calling procedure

19. June 18, 2001Systems Architecture II19 Activation Records (Frames) and the Call Stack An activation record (frame) is a segment on the stack containing a procedure’s saved registers and local variables. Each time a procedure is called a frame ($fp: frame pointer register points to the current frame) is placed on the stack.

20. June 18, 2001Systems Architecture II20 Compiler Linker Loader Translation Hierarchy

21. June 18, 2001Systems Architecture II21 Bits have no inherent meaning — conventions define relationship between bits and numbers Binary numbers (base 2) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001... decimal: 0...2 n -1 Complications: numbers are finite (overflow) fractions and real numbers negative numbers –e.g., no MIPS subi instruction; addi can add a negative number) How do we represent negative numbers? –Which bit patterns will represent which numbers? Numbers

22. June 18, 2001Systems Architecture II22 Sign Magnitude: One's Complement Two's Complement 000 = +0000 = +0000 = +0 001 = +1001 = +1001 = +1 010 = +2010 = +2010 = +2 011 = +3011 = +3011 = +3 100 = -0100 = -3100 = -4 101 = -1101 = -2101 = -3 110 = -2110 = -1110 = -2 111 = -3111 = -0111 = -1 Issues: balance, number of zeros, ease of operations Which one is best? Why? Possible Representations

23. June 18, 2001Systems Architecture II23 32 bit signed numbers: 0000 0000 0000 0000 0000 0000 0000 0000 two = 0 ten 0000 0000 0000 0000 0000 0000 0000 0001 two = + 1 ten 0000 0000 0000 0000 0000 0000 0000 0010 two = + 2 ten... 0111 1111 1111 1111 1111 1111 1111 1110 two = + 2,147,483,646 ten 0111 1111 1111 1111 1111 1111 1111 1111 two = + 2,147,483,647 ten 1000 0000 0000 0000 0000 0000 0000 0000 two = – 2,147,483,648 ten 1000 0000 0000 0000 0000 0000 0000 0001 two = – 2,147,483,647 ten 1000 0000 0000 0000 0000 0000 0000 0010 two = – 2,147,483,646 ten... 1111 1111 1111 1111 1111 1111 1111 1101 two = – 3 ten 1111 1111 1111 1111 1111 1111 1111 1110 two = – 2 ten 1111 1111 1111 1111 1111 1111 1111 1111 two = – 1 ten maxint minint MIPS

24. June 18, 2001Systems Architecture II24 Negating a two's complement number: invert all bits and add 1 –remember: “negate” and “invert” are quite different! Converting n bit numbers into numbers with more than n bits: –MIPS 16 bit immediate gets converted to 32 bits for arithmetic –copy the most significant bit (the sign bit) into the other bits 0010 -> 0000 0010 1010 -> 1111 1010 –"sign extension" (lbu vs. lb) Two's Complement Operations

25. June 18, 2001Systems Architecture II25 Just like in grade school (carry/borrow 1s) 0111 0111 0110 + 0110- 0110- 0101 Two's complement operations easy –subtraction using addition of negative numbers 0111 + 1010 Overflow (result too large for finite computer word): –e.g., adding two n-bit numbers does not yield an n-bit number 0111 + 0001 note that overflow term is somewhat misleading, 1000 it does not mean a carry “overflowed” Addition & Subtraction

26. June 18, 2001Systems Architecture II26 No overflow when adding a positive and a negative number No overflow when signs are the same for subtraction Overflow occurs when the value affects the sign: Detecting Overflow

27. June 18, 2001Systems Architecture II27 Addition and Subtraction Carry-ripple adder 0000 0111 + 0000 0110 0000 1101 0000 0111 0000 0111 0000 0110 0000 0110 - 0000 0110 +1111 1010 - 0000 0111 + 1111 1001 0000 0001 0000 0001 1111 1111 1111 1111

28. June 18, 2001Systems Architecture II28 Logical Operations Shift left << sll Shift right >> srl Shift right arithmetic sra Bitwise and & and, andi Bitwise or | or, ori Bitwise complement (not) ~ not (pseudo) Exclusive or ^ xor, xori

29. June 18, 2001Systems Architecture II29 Representation of Shift Instruction Example sll$t2, $s0, 8 # $t2 = $s0 << 8 $t2 = $8, $s0 = $16 000000 00000 10000 01010 01000 000000 op rs rt rd shamt func

30. June 18, 2001Systems Architecture II30 MIPS ALU

31. June 18, 2001Systems Architecture II31 Distribution of Floating Point Numbers 3 bit mantissa exponent {-1,0,1} 01 23

32. June 18, 2001Systems Architecture II32 Representation of Floating Point Numbers IEEE 754 single precision 313023220 SignBiased exponentNormalized Mantissa (implicit 24th bit) (-1) s  F  2 E-127

33. June 18, 2001Systems Architecture II33 Representation of Floating Point Numbers IEEE 754 double precision 313020190 SignBiased exponentNormalized Mantissa (implicit 53rd bit) (-1) s  F  2 E-1023

34. June 18, 2001Systems Architecture II34 Floating Point Addition Hardware

35. June 18, 2001Systems Architecture II35 Single Cycle Datapath & Control Implementation of MIPS Simplified to contain only: –memory-reference instructions: lw, sw –arithmetic-logical instructions: add, sub, and, or, slt –control flow instructions: beq, j Generic Implementation: –use the program counter (PC) to supply instruction address –get the instruction from memory –read registers –use the instruction to decide exactly what to do

36. June 18, 2001Systems Architecture II36 Timing Clocks used in synchronous logic – when should an element that contains state be updated? Edge-triggered timing cycle time rising edge falling edge

37. June 18, 2001Systems Architecture II37 Edge Triggered Timing State updated at clock edge read contents of some state elements, send values through some combinational logic write results to one or more state elements

38. June 18, 2001Systems Architecture II38 Components for Simple Implementation Functional Units needed for each instruction

39. June 18, 2001Systems Architecture II39 Datapath with Control

40. June 18, 2001Systems Architecture II40 Multicycle Implementation of MIPS Break up the instructions into steps, each step takes a cycle –balance the amount of work to be done –restrict each cycle to use only one major functional unit –Functional units: memory, register file, and ALU At the end of a cycle –Use internal registers to store results between steps

41. June 18, 2001Systems Architecture II41 Execution Steps 1Instruction fetch –IR = Memory[PC]; –PC = PC + 4; 2Instruction decode and register fetch –A = Reg[IR[25-21]]; –B = Reg[IR[20-16]]; –ALUOut = PC + (sign-extend (IR[15-0]) << 2);

42. June 18, 2001Systems Architecture II42 Execution Steps 3Execution, memory address computation, or branch completion –Memory reference ALUOut = A + sign-extend (IR[15-0]); –Arithmetic-logical instruction (R-type) ALUOut = A op B; –Branch if (A == B) PC = ALUOut; –Jump PC = PC [31-28] || (IR[25-0]<<2)

43. June 18, 2001Systems Architecture II43 Execution Steps 4Memory access or R-type instruction completion –memory reference MDR = Memory [ALUOut]; –or Memory [ALUOut] = B; –R-type completion Reg [IR[15-11]] = ALUOut; 5Memory read completion –Reg [IR[20-16]] = MDR;

44. June 18, 2001Systems Architecture II44 Finite State Machine Set of states Next function determined by input and current state Output determined by current state and possibly input Moore machine (output determined only by current state)

45. June 18, 2001Systems Architecture II45 Multicycle Datapath with Exception Support

46. June 18, 2001Systems Architecture II46 Multicycle Control with Exceptions

47. June 18, 2001Systems Architecture II47 Implementation