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ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 1 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Bruce Mayer, PE Registered.

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Presentation on theme: "ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 1 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Bruce Mayer, PE Registered."— Presentation transcript:

1 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 1 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Bruce Mayer, PE Registered Electrical & Mechanical Engineer BMayer@ChabotCollege.edu Engineering 43 FETs-2 (Field Effect Transistors)

2 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 2 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Learning Goals  Understand the Basic Physics of MOSFET Operation  Describe the Regions of Operation of a MOSFET  Use the Graphical LOAD-LINE method to analyze the operation of basic MOSFET Amplifiers  Determine the Bias-Point (Q-Point) for MOSFET circuits

3 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 3 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Load Line: Common Source Amp  Shown below is typical “Common- Source” Amplifier circuit  THE DC sources, V DD & V GG bias the MOSFET for Amp operation  That is, the two DC sources set The Operating, or Q, Pt  Now apply KVL to left loop

4 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 4 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Load Line: Common Source Amp  Using the values given the Schematic  Now KVL on Right Loop  Rearranging  Of form: y = mx + b  Using given values

5 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 5 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Load Line: Common Source Amp  Thus the LoadLine Equation  Plot this on the FET vi Curve to determine the Operating Point  Since this is a LINE need only 2-points Intercepts are easy  Making a T-Table

6 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 6 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Draw LoadLine on FET vi Curve V GG = V GS sets Q-Pt

7 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 7 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Max and Min Opp-Points  The common source Amp is designed to Operate in the SATURATION Region. Recall the v GS Eqn  By sin behavior  Reading the vi-LL graph find (v DS,i D ) co-ords (v DS,i D ) max = (4V,16mA) –v GS = 5V (v DS,i D ) min = (16V,4mA) –v GS = 3V

8 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 8 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Voltage Swing  The common source Amp is must stay in Saturation. For this nFET that means max & min v GS values of 5V & V to given the 1V amplitude of the sin  From Last Slide We calculated corresponding Xmax/min values for v DS v DS,min = 4V (v GS = 5) v DS,max = 16V (v GS = 3)  Note that the output direction is Opposite the Input direct  The ckt produces a SATURATED output Voltage Swing of 4V-16V = −12V

9 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 9 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Input and OutPut Compared  Note that OUTput peaks occur at INput Valleys → Inversion  The ratio of the V-swings  This NOT the Gain, A v = v in /v out Gate Excitation v DS Response

10 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 10 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis LoadLine Gain  Notice v GS : 4→3 –V DS : 11→15 (∆ = 4) v GS : 4→5 –V DS : 11→4 (∆ = 7)  This is due to the NONlinear nature of MOSFETS; they are “Square-Law” devices The i D lines in SAT are not evenly Spaced

11 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 11 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis LoadLine Gain  Since the FET is NOT linear, v out is NOT directly proportional to v in, so we can NOT Define a true Gain  “Small Signal” methods WILL allow us to define a true grain for the AC part of the voltage input Requires Calculus –To “Linearize” ckt

12 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 12 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Common-Source Amp Analysis  To analyze this amplifier we will do the following: 1.Perform DC analysis (find bias, or Q, point; i.e., find the DC drain current and check that the transistor is in the saturation region) 2.Find circuit small-signal AC model (based on the bias point obtained) 3.Perform AC (small signal) analysis

13 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 13 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Saturation Slippery-Slope  Must also take care that the small-signal input does NOT push the FET Out of Saturation at ANY Time.  The v in -Amplitude and Bias-Pt Selection could Drive the FET out of SAT and into TRIODE Operation Drive the FET into CutOff (v GS < V to )

14 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 14 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis One-Supply Bias Circuit  Usually only ONE supply voltage is available. In this case set V G with a voltage divider  By Thevenin  Since the Gate on a IGFET draws NO current, we have a simple voltage divider on the Left thru R 1 & R 2.  Thus V G to GND

15 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 15 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis One-Supply Bias Circuit  Replacing the left side of the ckt with its V-Divider equivalent  Then the KVL Eqn for the Gate Loop  The is NO V-Drop across R G as i G = 0  Thus  Recall the CE amp is designed to operate in Saturation which produces i D at this level

16 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 16 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis One-Supply Bias Circuit  If the Circuit has been properly Biased the FET is in SATURATION  In Saturation i D is independent of v DS and equals, at the operating, or Q, point  Recall the KVL eqn on the GATE Loop (now Assumed at the “Q” point):  Sub into SAT eqn

17 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 17 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis One-Supply Bias Circuit  Solve for v GSQ :  Or:  Introduce new Constant:  Yields quadratic Eqn in v GSQ :  Now Solve by MATLAB’s MuPAD

18 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 18 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis v GSQ by MuPAD

19 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 19 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis One-Supply Bias Circuit  Discarding the Negative Root find  Then Find i DQ by subbing v GSQ from above into the gate KVL Eqn:

20 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 20 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis One-Supply Bias Circuit  Solving the last two eqns yields i DQ and v GSQ Beware that the parabolic i D eqn will produce an extraneous root –Discard the SMALLER root as SAT requires: v GS −V to ≥ 0  The KVL eqn on ckt Right-Side  ReArranging  Then with i DQ from before (MuPAD)

21 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 21 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Small Signal FET Model  At the Operating Point the quantities are DC, and should be Noted in Upper case letters:  If a small-amplitude ac signal is injected into the circuit the instantaneous quantity Eqns:  Where i d and v gs are the small signal quantities  A conceptual Diagram

22 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 22 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Small Signal FET Model  Recall i D in SAT  From last slide  Subbing for i D & v GS  Now the Q-Pt is also in Saturation so,  Using this reln and expanding the I DQ +i d eqn yields  Where g m is called the “small signal transconduce” for an nMOSFET  Again for IGFET

23 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 23 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Small Signal FET Model  These eqns describe the linear small signal operation in the Saturation region  A graphical representation of the model

24 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 24 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis gm(Q)  Usually a greater value of g m is better than a smaller one  g m is a function of the Device “K” Parameter and the Q-Pt values  Recall  Also recall at Q-Pt  Or:  Thus  Simplifying:  Recall from our MOSFET Construction Discussion “KP” is single quantity

25 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 25 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis gm(Q)  Using  And  Find  Simplifying  Thus to increase the transconductance of a KP-fixed MOSFET Increase I DQ –Remember, V swing must be entirely in the SATURATION region Increase the W/L ratio –But this makes the transistor BIGGER; usually NOT desired

26 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 26 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Refined Small Signal Model  The previous model assumed CONSTANT i D in Saturation  Real MOSFETs exhibit an upward Slope in SAT:  Recall that a SLOPE on a vi Curve is effectively A Conductance; G or g An inverse Resistance 1/R or 1/r  On a MOSFET this slope is called the “Drain Resistance, r d

27 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 27 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Refined Small Signal Model  The KCL Equation for the model that accounts for the upward i D Slope in SAT  The Graphical Representation

28 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 28 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis gm & rd by Calculus  Start with Refined Model Equation  ReCall G & g in Siemens (amps per volt)  Now let the ∆’s approach ZERO to make derivatives  Specifically find the slope of model eqn when v ds = 0  Thus g m :  Note that MOSFET operates at the Q-Pt

29 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 29 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis gm & rd by Calculus  Again use approx:  In the this case v ds = 0 implies v DS = V DSQ so can approximate:  This Eqn is an approximation of a derivation amongst i D, v GS and v DS G & g in Siemens (amps per volt)  Now let the ∆’s approach ZERO to make derivatives  Again letting the ∆’s go to zero  Recall  Now in the small- signal eqn let v gs = 0

30 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 30 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis gm & rd by Calculus  Solving this Eqn for r d  In this Case  Again use approx:  Thus similar to before  Thus we can write a partial derivative for r d  Or, as stated in the Text Book

31 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 31 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Example 12.3: Find g m & r d Q-Pt → (V DSQ, I DQ ) = (10 V, 7.4 mA) Also V GSQ = 3.5 V

32 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 32 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Example 12.3: Find gm & rd  Recall approx.  In This Example V DSQ = 10 V  Make a t-Table when v DS = 10V See vi Graph  Thus ∆v GS = (4 − 3) V = 1V ∆i D = (10.7 − 4.7) mA = 6mA  Then g m :

33 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 33 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Example 12.3: Find gm & rd  Recall approx.  In This Example V GSQ = 3.5 V  Make a t-Table when v GS = 3.5V See vi Graph  Thus ∆v DS = (14 − 4) V = 10V ∆i D = (8 − 6.7) mA = 1.3mA  Then r d :

34 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 34 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Example 12.3: Find g m & r d Q-Pt → (V DSQ, I DQ ) = (10 V, 7.4 mA) Also V GSQ = 3.5 V Δv DS ΔiDΔiD

35 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 35 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis All Done for Today Large Scale Resistance Challenge

36 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 36 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis All Done for Today 3 & 4 Connection nFET

37 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 37 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Bruce Mayer, PE Registered Electrical & Mechanical Engineer BMayer@ChabotCollege.edu Engineering 43 Appendix

38 BMayer@ChabotCollege.edu ENGR-43_Lec-12b_FETs-2_LoadLine_Analysis.pptx 38 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis DC Srcs  SHORTS in Small-Signal  In the small-signal equivalent circuit DC voltage-sources are represented by SHORT CIRUITS; since their voltage is CONSTANT, the exhibit ZERO INCREMENTAL, or SIGNAL, voltage  Alternative Statement: Since a DC Voltage source has an ac component of current, but NO ac VOLTAGE, the DC Voltage Source is equivalent to a SHORT circuit for ac signals

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