1. Technical University Tallinn, ESTONIA 1 Faults in Circuits and Fault Diagnosis 0110 T 6 0010011 FaultF 5 located Fault table Test experiment Test generation Fault simulation Fault diagnosis Fault modeling Testing How many rows and columns should be in the Fault Table?

2. Technical University Tallinn, ESTONIA 2 Sequential Fault Diagnosis Sequential fault diagnosis by Edge-Pin Testing Two faults F 1,F 4 remain indistinguishable Not all test patterns used in the fault table are needed Different faults need for identifying test sequences with different lengths The shortest test contains two patterns, the longest four patterns Diagnostic tree:

3. Technical University Tallinn, ESTONIA 3 Stuck-at Faults and their Properties Fault equivalence and fault dominance: & A B C D A B C D Fault class 1 1 1 0 A/0, B/0, C/0, D/1 Equivalence class 0 1 1 1 A/1, D/0 1 0 1 1 B/1, D/0 Dominance classes 1 1 0 1 C/1, D/0 & Fault collapsing: &  1 1 1  1 1 Dominance 1  0 0 Equivalence & & 1  0 0 1  1 1  0 0 Dominance Equivalence

4. Technical University Tallinn, ESTONIA 4 Gate-Level Test Generation Single path fault propagation: & & & & & & & 1 2 3 4 5 6 7 7171 7272 7373 a b c d e y Macro D D D D D 1 1 1 1 Fault sensitisation: x 7,1 = D Fault propagation: x 2 = 1, x 1 = 1, b = 1, c = 1 Line justification: x 7 = D = 0: x 3 = 1, x 4 = 1 b = 1: (already justified) c = 1: (already justified) Symbolic fault modeling: D = 0 - if fault is missing D = 1 - if fault is present 1 1 1 1 Test pattern

5. Technical University Tallinn, ESTONIA 5 Testing of Inputs 1 & & 1 a b y a1a1 b a2a2 11 0 1 No test for  0 0 & & 1 a b y a1a1 b a2a2 10 1 1 No test for  1 0 & & 1 a b y a1a1 b a2a2 00 1 1 Test for  1

6. Technical University Tallinn, ESTONIA 6 Testing of Inputs 1 & & 1 a b y a1a1 b a3a3 1 1 0 1 No test for  0 & c a2a2 c 0 0

7. Technical University Tallinn, ESTONIA 7 Boolean derivatives Boolean function: Y = F(x) = F(x 1, x 2, …, x n ) Boolean partial derivative:

8. Technical University Tallinn, ESTONIA 8 Boolean Derivatives Useful properties of Boolean derivatives: These properties allow to simplify the Boolean differential equation to be solved for generating test pattern for a fault at x i If F(x) is independent of x i Näide:

9. Technical University Tallinn, ESTONIA 9 Calculation of Boolean Derivatives Given: Calculation of the Boolean derivative:

10. Technical University Tallinn, ESTONIA 10 Derivatives for complex functions Boolean derivative for a complex function: Example: Additional condition:

11. Research in ATI © Raimund Ubar BDDs and Testing of Logic Circuits By the BDD for F(X) we can generate test patterns only for testing inputs 11 How about testing the internal nodes of the circuit?  SSBDD The tasks on BDDs: (1)Pattern simulation (analysis) (2)Pattern generation (synthesis)

12. Technical University Tallinn, ESTONIA 12 x1x1 x2x2 y x3x3 x2x2 x4x4 x1x1 x4x4 x5x5 x2x2 x6x6 x1x1 x2x2 1 0 Test Generation with BD and BDD BD: BDD: x1x1 x2x2 x3x3 x4x4 x5x5 x6x6 y 01-0D-D Test pattern:

13. Research in ATI © Raimund Ubar 13 & & & 1 & x1x1 x2x2 x3x3 x4x4 y Test generation for: x11x11 x 21 x12x12 x 31 x13x13 x 22 x 32 x 11  0 1010 1 0 0 0 0 1010 1010 0 x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 1 11 1010 Structural BDD: x1x1 y x2x2 x4x4 x3x3 x2x2 Functional BDD: 0 1 1 1010 1 1 x 1 x 2 x 3 x 4 y 1 1 0 - Test pattern: 1  0 Test generation for: x10x10 BDDs and Test Generation ALGORITHM: Begin TG with Functional BDD Simulate the test on Structural BDD Update the test on Structural BDD

14. Technical University Tallinn, ESTONIA Example: Test Generation with SSBDDs & & & 1 & x1x1 x2x2 x3x3 x4x4 y x 1 x 2 x 3 x 4 y 0 0 1 1 0 Testing Stuck-at-1 faults on paths: Test pattern: x11x11 x 21 x12x12 x 31 x13x13 x 22 x 32 Tested faults: x 12  1, x 22  1 Not tested: x 11  1 x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 1 0 1 1

15. Research in ATI © Raimund Ubar Algorithm: 1.Determine the activated path to find the fault candidates 2.Analyze the detectability of the each candidate fault (each node represents a subset of real faults) Fault Analysis with SSBDDs x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 0 1 0 1 15 & & & 1 & x1x1 x2x2 x3x3 x4x4 y x11x11 x 21 x12x12 x 31 x13x13 x 22 x 32 0 1 0 0 0 1 0 0

16. Research in ATI © Raimund Ubar Fast and Simple Test Generation Test generation by using disjunctive normal forms & & & 1 & x1x1 x2x2 x3x3 x4x4 y x11x11 x 21 x12x12 x 31 x13x13 x 22 x 32

17. Technical University Tallinn, ESTONIA Pseudoexhaustive Test Optimization Output function verification (partial parallelity) x1x1 x2x2 x3x3 x4x4 F 1 (x 1, x 2 ) F 2 (x 1, x 3 ) F 3 (x 2, x 3 ) F 4 (x 2, x 4 ) F 5 (x 1, x 4 ) F 6 (x 3, x 4 ) 0011 0101 F1F1 F2F2 F3F3 Exhaustive testing - 16 Pseudo-exhaustive, full parallel – 4 (not possible) Pseudo-exhaustive, partially parallel - 6 01 10 00 1 F4F4 1 - 0- 0 F5F5 1 0

18. Research in ATI © Raimund Ubar Multiple Fault Testing The problem arised: Fault Masking  &  & 1/0  1 1 0/1 1/0 1 1 0 0/1 a b c d Multiple fault F may be not detected by a complete test T for single faults because of circular masking among the faults in F Test pattern set T = {1111, 0111, 1110, 1001, 1010, 0101} detects every single fault The only test for detecting b  1 or c  1 is 1001 However, b  1 masks c  1 and c  1 masks b  1

19. Research in ATI © Raimund Ubar Test Pairs for Multiple Fault Testing To test a path under any multiple faults, two pattern test is needed  &  & 0  11 11/00 10/11 01/00 0101 00 a b c d Testing of multiple faults by pairs of patterns b  1 11 Tested path for b  1/0 00/11 11/11 The lower path from b is under test A pair of patterns is applied on b There is a masking fault c  1 0101 c  1 1 st pattern: fault b  1 is masked Either the fault on the path is detected or the masking fault is detected No error Error 2 nd pattern: fault c  1 is detected The secret: 1st pattern tests b 2nd pattern tests c

20. Technical University Tallinn, ESTONIA Critical Path Tracing & & 1 1 1 2 3 4 5 a c b 1 1 0 0 0 0 0 1 1 y 12 34 5 y Problems : & & 1 1 1 1/01/0 y & & 1 0 1 1 y 1/0 1 1 1 1 The critical path is not continuous The critical path breaks on the fan-out

21. Research in ATI © Raimund Ubar Algorithm: 1.Determine the activated path to find the fault candidates 2.Analyze the detectability of the each candidate fault (each node represents a subset of real faults) Fault Analysis with SSBDDs x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 0 1 0 1 21 & & & 1 & x1x1 x2x2 x3x3 x4x4 y x11x11 x 21 x12x12 x 31 x13x13 x 22 x 32 0 1 0 0 0 1 0 0

22. Technical University Tallinn, ESTONIA Fault Simulation with Boolean Derivatives & 1 x1x1 y 1011 1110 1001 1011 Detected faults vector: - 10 - T1: No faults detected T2: x 1  1 detected T3: x 1  0 detected T4: No faults detected x3x3 x2x2 Simulation approaches: 1)Single fault simulation 2)Parallel fault simulation for a subset of test patterns (by extending bit- operations to operations with computer words) 3)Iterative fault simulation for subsets of faults (by creating transitive closures – deductive simulation and critical path tracing) 4)Parallel fault simulation for both, patterns and faults

23. Technical University Tallinn, ESTONIA Parallel Critical Path Tracing & 1 x1x1 y 1011 1110 1001 1011 Detected faults vector: - 10 - T1: No faults detected T2: x 1  1 detected T3: x 1  0 detected T4: No faults detected x3x3 x2x2 Handling of fanout points: Fault simulation Boolean differential calculus x y xkxk x2x2 x1x1 F

24. Research in ATI © Raimund Ubar Synthesis of Functional HLDDs Data Flow Diagram/FSMD Begin A = B + C x A A =  A + 1 B = B + C x A B =  BC =  C x B  C x C A = A +  B + C x C C = A + B A =  C + B END 0 0 0 0 0 1 1 1 1 1 Constraints Assignment statements qxAxA xBxB xCxC 0 A = B + C; q = 1 10 A = A + 1; q = 4 11 B = B + C; q = 2 20 C = A + B; q = 5 21 C = C; q = 3 30 C = A + B; q = 5 31 A = C + B; q = 5 40 B = B 400 A = A + B + C; q = 5 401 q = 5 41 C = C; q = 5 Results of cycle based symbolic simulation: q = 0 q = 1 q = 2 q = 3 q = 4 q = 5

25. Research in ATI © Raimund Ubar Synthesis of HLDDs Constraints Assignment statements qxAxA xBxB xCxC 0 A = B + C; q = 1 10 A = A + 1; q = 4 11 B = B + C; q = 2 20 C = A + B; q = 5 21 C = C; q = 3 30 C = A + B; q = 5 31 A = C + B; q = 5 40 B = B 400 A = A + B + C; q = 5 401 q = 5 41 C = C; q = 5 Results of symbolic simulation: qxAxA xBxB xCxC A 0B + C 10 A + 1 31 C + B 400 A + B + C Extraction of the behaviour for A: A = f (q, A, B, C, x A, x C ) = = (q=0)(B+C)  (q=1)(x A =0) (  A + 1)  (q=3)(x C =1)(  C+B)  (q=4)(x A =0)(x C =0)(A+  B + C + 1) Predicate equation for A:

26. Research in ATI © Raimund Ubar Synthesis of HLDDs qxAxA xBxB xCxC A 0B + C 10 A + 1 31 C + B 400 A + B + C Extraction of the behaviour for A: A = (q=0)(B+C)  (q=1)(x A =0) (  A + 1)  (q=3)(x C =1)(  C+B)  (q=4)(x A =0)(x C =0)(A+  B + C + 1) Predicate equation for A: Decision diagram for A: Synthesis method: similar to Shannon’s expansion theorem:

27. Technical University Tallinn, ESTONIA High-Level Decision Diagrams Superposition of High- Level DDs: A single DD for a subcircuit Instead of simulating all the components in the circuit, only a single path in the DD should be traced y 4 y 3 y 1 R 1 + R 2 IN + R 2 R 1 * R 2 IN* R 2 y 2 R 2 0 1 2 0 1 0 1 0 1  0 R 2 IN R 1 2 3 R2R2 R 2 + M 3 M1M1 M2M2

28. Technical University Tallinn, ESTONIA Test Generation for Digital Systems y 4 y 3 y 1 R 1 +R 2 IN+ R 2 R 1 *R 2 IN*R 2 y 2 R 2 0 1 2 0 1 0 1 0 1  0 R 2 IN R 1 2 3 Multiple paths activation in a single DD Control function y 3 is tested Data path Decision Diagram High-level test generation with DDs: Conformity test Control: For D = 0,1,2,3: y 1 y 2 y 3 y 4 = 00D2 Data: Solution of R 1 + R 1  IN  R 1  R 1 * R 1 Test program:

29. Technical University Tallinn, ESTONIA Test Generation for Digital Systems y 4 y 3 y 1 R 1 +R 2 IN+ R 2 R 1 *R 2 IN*R 2 y 2 R 2 0 1 2 0 1 0 1 0 1  0 R 2 IN R 1 2 3 Single path activation in a single DD Data function R 1 * R 2 is tested Data path Decision Diagram High-level test generation with DDs: Scanning test Control: y 1 y 2 y 3 y 4 = 0032 Data: For all specified pairs of (R 1, R 2 ) Test program:

30. Technical University Tallinn, ESTONIA Decision Diagrams for Microprocessors I 1 :MVI A,DA  IN I 2 :MOV R,AR  A I 3 :MOV M,ROUT  R I 4 :MOV M,AOUT  IA I 5 :MOV R,MR  IN I 6 :MOV A,MA  IN I 7 :ADD RA  A + R I 8 :ORA RA  A  R I 9 :ANA RA  A  R I 10 :CMA A,DA   A Instruction set: IA 2 R IN 5 R 1,3,4,6-10 AIIN 1,6 IN 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 IR 3 A OUT 4 DD-model of the microprocessor:

31. Technical University Tallinn, ESTONIA Decision Diagrams for Microprocessors High-Level DD-based structure of the microprocessor (example): DD-model of the microprocessor: OUT R A IN I IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 A + R

32. Technical University Tallinn, ESTONIA Test Program Synthesis for Microprocessors Scanning test program for adder: Instruction sequence T = I 5 (R)I 1 (A)I 7 I 4 for all needed pairs of (A,R) OUT I4I4 A I7I7 A R I1I1 IN(2) IN(1) R I5I5 Time: t t - 1 t - 2 t - 3 Observation Test Load Test program: For j=1,n Begin I 5 : Load R = IN(j 1 ) I 1 : Load A = IN(j 2 ) I 7 : ADD A = A + R I 4 : Read A End IN(j 1 ) IN(j 2 )A Test data Test results

33. 0 M1M1 R0R0 A1A1 R0R0 R1R1 A1A1 R0R0 R2R2 A1A1 R0R0 1 2 M1M1 y1y1 0 IN 0 y2y2 A B A+B 1 2 A-B 3 1 0 OUT y3y3 A2A2 R0R0 B y3y3 B R1R1 R1R1 1 2 0 1 A y3y3 2 RISC Processor and its HLDD model Register block Output behaviour ALU

34. 0 M1M1 R0R0 A1A1 R0R0 R1R1 A1A1 R0R0 R2R2 A1A1 R0R0 1 2 M1M1 y1y1 0 IN 0 y2y2 A B A+B 1 2 A-B 3 1 0 OUT y3y3 A2A2 R0R0 B y3y3 B R1R1 R1R1 1 2 0 1 A y3y3 2 0 y3y3 A2A2 R0R0 y3y3 B R1R1 R2R2 1 2 0 1 0 M1M1 A1A1 A1A1 A1A1 1 2 y1y1 0 IN 0 y2y2 A B A+B 1 2 A-B 3 1 A y3y3 2 RISC Processor and its HLDD model Network level model System level model

35. 0 OUT y3y3 A2A2 R0R0 y3y3 B R1R1 R2R2 1 2 0 1 0 M1M1 A1A1 A1A1 A1A1 1 2 y1y1 0 IN 0 y2y2 A B A+B 1 2 A-B 3 1 A y3y3 2 0 OUT y3y3 A2A2 R0R0 y3y3 B R1R1 R2R2 1 2 0 1 0 M1M1 A1A1 A1A1 A1A1 1 2 y1y1 0 IN 0 y2y2 A B A+B 1 2 A-B 3 1 A y3y3 2 Ty1y1 y2y2 y3y3 A1A1 A2A2 INR0R0 R1R1 R2R2 BAOUT 110D1 Ty1y1 y2y2 y3y3 A1A1 A2A2 INR0R0 R1R1 R2R2 BAOUT 200210D1 Test Program Generation: Test 1 Test step 1: Load R 0 Test step 2: Testing ALU (M1 = A, Transfer A to R 1 )

36. 0 OUT y3y3 A2A2 R0R0 y3y3 B R1R1 R2R2 1 2 0 1 0 M1M1 A1A1 A1A1 A1A1 1 2 y1y1 0 IN 0 y2y2 A B A+B 1 2 A-B 3 1 A y3y3 2 0 OUT y3y3 A2A2 R0R0 y3y3 B R1R1 R2R2 1 2 0 1 0 M1M1 A1A1 A1A1 A1A1 1 2 y1y1 0 IN 0 y2y2 A B A+B 1 2 A-B 3 1 A y3y3 2 Ty1y1 y2y2 y3y3 A1A1 A2A2 INR0R0 R1R1 R2R2 BAOUT 31021D2D1 D2D1 Ty1y1 y2y2 y3y3 A1A1 A2A2 INR0R0 R1R1 R2R2 BAOUT 41102D3 D1D2 Test step 3: Read R 1 Load R 2 Test Program Generation: Test 1/2 Test Program Generation: Test 2 Test step 4: Load B, Load R 0

37. Test step Control partData part y1y1 y2y2 y3y3 A1A1 A2A2 INR0R0 R1R1 R2R2 BA OUT 110D1 200210 31021D2 D1 41102D3 D2 501011 602202D5D2 71010D4 D5 803222D6D4 902D6 Fault cove- rage 2/24/43/3 4332134 Full Test Program and High Level Fault Table