1. 1 Sequential Digital Circuits Alexander Titov 11 October 2014

2. 2 Intel Laboratory at Moscow Institute of Physics and Technology MIPT-MIPS 2014 Project Layers of Abstraction in Computes Science (CS) Application Algorithms Programming Language Operating System Instruction Set Architecture Microarchitecture Gates/Register-Transfer Level (RTL) Circuits Physics Topics of this lecture

3. 3 Intel Laboratory at Moscow Institute of Physics and Technology MIPT-MIPS 2014 Project But, combinational circuits have a significant limitation: they cannot remember any information Refresher: Combinational vs. Sequential Circuits If the output of a function is completely defined by the current input then the function is called combinational: Q t = F(x t, y t, z t, …) Combinational circuit (scheme) is an implementation of a combinational function A lot of things can be implemented using combinational circuits Just a few examples that we already know: summator, decoder, multiplexer But, combinational circuits have a significant limitation:

4. 4 Intel Laboratory at Moscow Institute of Physics and Technology MIPT-MIPS 2014 Project Sequential Circuits Sequential circuits are able to store information If the output of a function depends not only on the current input, but on the previous state, then the function is called sequential Q t = F(x t, y t, z t, …, Q t-1 ) F(x t-1, y t-1, z t-1, …, Q t- 2 )) F(x t-2, y t-2, z t-2, …, Q t- 3 ))) Sequential circuit is an implementation of a sequential function Their main advantage is ability to remember the previous state Any circuit with memory is a sequential circuits

5. 5 Intel Laboratory at Moscow Institute of Physics and Technology MIPT-MIPS 2014 Project SR Flip-Flop SRQ t-1 Qt xyout 001 010 100 110 Q !Q x y out y ≡ x y 0 ≡ Q !Q reset set 0 0 1 0 1 1 0 1 NOR: SR flip-flop: o The simplest store element: o SR flip-flop: 0 1 00QQ 01Q0 10Q1 11Q0 reset set Q !Q Prohibited state

6. 6 Intel Laboratory at Moscow Institute of Physics and Technology MIPT-MIPS 2014 Project SR Flip-Flop reset set Q !Q R S Q SRQ t-1 Qt 00QQ 01Q0 10Q1 11Q0 S 0 1 R 0 1 Q 0 1 !Q 0 1 ? ? But, which signal will be really faster will depend on many factors (e.g., temperature). The output will be determined by the fastest signal

7. 7 Intel Laboratory at Moscow Institute of Physics and Technology MIPT-MIPS 2014 Project D Flip-Flop Don’t have prohibited states Asserted by a level of the write enable signal (we) Store one bit of information Can be used as building block for creating static memory arrays S QR !Q Write enable Data D we Q D Q t-1 Qt D0QQ 01Q0 11Q1

8. 8 Intel Laboratory at Moscow Institute of Physics and Technology MIPT-MIPS 2014 Project Trigger asserted by edge Don’t open for writing neither at we =0 nor at we =1 as one of the triggers is closed It is open for a very small amount of time when the write enable goes from 0 to 1 The value from the first trigger is written to the second trigger and then the first trigger is closed It is a trigger asserted by the positive edge of write enable signal Such types of triggers are mostly used to organize pipelined execution D we Q D Q out Write enable Data DweQ t-1 Qt D Q we D0QQ D1QQ D ↑ QD D ↓ QQ

9. 9 Intel Laboratory at Moscow Institute of Physics and Technology MIPT-MIPS 2014 Project Single port 2^MxN Memory Array Memory Array address input data output data M N N Write enable

10. 10 Intel Laboratory at Moscow Institute of Physics and Technology MIPT-MIPS 2014 Project Single port 4x1 Memory Array Memory Array address input data output data 2 1 1 Write enable

11. 11 Intel Laboratory at Moscow Institute of Physics and Technology MIPT-MIPS 2014 Project Single port 4x1 Memory Array Multiplexer Decoder Write control

12. 12 Intel Laboratory at Moscow Institute of Physics and Technology MIPT-MIPS 2014 Project Single port 4x2 Memory Array Multiplexer bit[0] Decoder Write control Multiplexer bit[1]

13. Critical paths 13

14. 14 Intel Laboratory at Moscow Institute of Physics and Technology MIPT-MIPS 2014 Project What is a critical path of scheme? Critical path is the slowest logic path in the circuit Reliable result of whole logic path can not be ready until critical path is passed by signal

15. 15 Intel Laboratory at Moscow Institute of Physics and Technology MIPT-MIPS 2014 Project Example of critical path finding: Multiplexer

16. Thank You Q/A 16