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Lecture 1: Circuits & Layout
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Outline A Brief History CMOS Gate Design Pass Transistors
CMOS Latches & Flip-Flops Standard Cell Layouts Stick Diagrams 1: Circuits & Layout
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The First Computer The Babbage Difference Engine (1832) 25.000 parts
cost: £17.470 1: Circuits & Layout
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ENIAC – The First Electronic Computer (1946)
1: Circuits & Layout
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The Transistor Revolution
Fi First Transistor Bell Labs 1948 1: Circuits & Layout
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Courtesy Texas Instruments
A Brief History 1958: First integrated circuit Flip-flop using two transistors Built by Jack Kilby at Texas Instruments 2010 Intel Core i7 mprocessor 2.3 billion transistors 64 Gb Flash memory > 16 billion transistors Courtesy Texas Instruments [Trinh09] © 2009 IEEE. 1: Circuits & Layout
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First Integrated Circuits
Bipolar Logic 1960’s ECL 3-input NAND Gate Motorola 1: Circuits & Layout
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Intel 4004 Microprocessor 1971 1000 transistors 1 MHz operation
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Growth Rate 53% compound annual growth rate over 50 years
No other technology has grown so fast so long Driven by miniaturization of transistors Smaller is cheaper, faster, lower in power! Revolutionary effects on society [Moore65] Electronics Magazine 1: Circuits & Layout
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Annual Sales >1019 transistors manufactured in 2008
1 billion for every human on the planet 1: Circuits & Layout
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Invention of the Transistor
Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable 1947: first point contact transistor John Bardeen and Walter Brattain at Bell Labs See Crystal Fire by Riordan, Hoddeson AT&T Archives. Reprinted with permission. 1: Circuits & Layout
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Transistor Types Bipolar transistors npn or pnp silicon structure
Small current into very thin base layer controls large currents between emitter and collector Base currents limit integration density Metal Oxide Semiconductor Field Effect Transistors nMOS and pMOS MOSFETS Voltage applied to insulated gate controls current between source and drain Low power allows very high integration 1: Circuits & Layout
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MOS Integrated Circuits
1970’s processes usually had only nMOS transistors Inexpensive, but consume power while idle 1980s-present: CMOS processes for low idle power Intel Museum. Reprinted with permission. [Vadasz69] © 1969 IEEE. Intel bit SRAM Intel bit mProc 1: Circuits & Layout
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Moore’s Law In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months 1: Circuits & Layout
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Moore’s Law: Then 1965: Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale Transistor counts have doubled every 26 months Integration Levels SSI: 10 gates MSI: gates LSI: 10,000 gates VLSI: > 10k gates [Moore65] Electronics Magazine 1: Circuits & Layout
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And Now… 1: Circuits & Layout
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Evolution in Complexity
1: Circuits & Layout
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Feature Size Minimum feature size shrinking 30% every 2-3 years
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Die Size Growth 1: Circuits & Layout
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Corollaries Many other factors grow exponentially
Ex: clock frequency, processor performance 1: Circuits & Layout
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Power Dissipation 1: Circuits & Layout
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Power density too high to keep junctions at low temp
10000 Rocket Nozzle 1000 Nuclear Reactor Power Density (W/cm2) 100 8086 10 Hot Plate 4004 P6 8008 8085 Pentium® proc 386 286 486 8080 1 1970 1980 1990 2000 2010 Year Power density too high to keep junctions at low temp Courtesy, Intel
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Complexity outpaces design productivity
Productivity Trends Logic Transistor per Chip (M) 10,000,000 10,000 1,000 100 10 1 0.1 0.01 0.001 100,000,000 0.01 0.1 1 10 100 1,000 10,000 100,000 Logic Tr./Chip 1,000,000 10,000,000 Tr./Staff Month. 100,000 1,000,000 Complexity 58%/Yr. compounded 10,000 (K) Trans./Staff - Mo. Productivity 100,000 Complexity growth rate 1,000 10,000 x x 100 1,000 x x 21%/Yr. compound x x x Productivity growth rate x 10 100 1 10 2003 1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 2001 2005 2007 2009 Source: Sematech Complexity outpaces design productivity Courtesy, ITRS Roadmap
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Why Scaling? Technology shrinks by 0.7/generation
With every generation can integrate 2x more functions per chip; chip cost does not increase significantly Cost of a function decreases by 2x But … How to design chips with more and more functions? Design engineering population does not double every two years… Hence, a need for more efficient design methods Exploit different levels of abstraction
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Design Metrics How to evaluate performance of a digital circuit (gate, block, …)? Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function
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Cost of Integrated Circuits
NRE (non-recurrent engineering) costs design time and effort, mask generation one-time cost factor Recurrent costs silicon processing, packaging, test proportional to volume proportional to chip area
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NRE Cost is Increasing
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Die Cost Wafer Going up to 12” (30cm) Single die
From
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Cost per Transistor cost: ¢-per-transistor 1 Fabrication capital cost per transistor (Moore’s law) 0.1 0.01 0.001 0.0001 1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012
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Yield
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Defects a is approximately 3
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Some Examples (1994) Chip Metal layers Line width Wafer cost Def./ cm2
Area mm2 Dies/wafer Yield Die cost 386DX 2 0.90 $900 1.0 43 360 71% $4 486 DX2 3 0.80 $1200 81 181 54% $12 Power PC 601 4 $1700 1.3 121 115 28% $53 HP PA 7100 $1300 196 66 27% $73 DEC Alpha 0.70 $1500 1.2 234 53 19% $149 Super Sparc 1.6 256 48 13% $272 Pentium 1.5 296 40 9% $417
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CMOS Gate Design Activity: Sketch a 4-input CMOS NOR gate
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Complementary CMOS Complementary CMOS logic gates
nMOS pull-down network pMOS pull-up network a.k.a. static CMOS Pull-up OFF Pull-up ON Pull-down OFF Z (float) 1 Pull-down ON X (crowbar) 1: Circuits & Layout
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Series and Parallel nMOS: 1 = ON pMOS: 0 = ON Series: both must be ON
Parallel: either can be ON 1: Circuits & Layout
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Conduction Complement
Complementary CMOS gates always produce 0 or 1 Ex: NAND gate Series nMOS: Y=0 when both inputs are 1 Thus Y=1 when either input is 0 Requires parallel pMOS Rule of Conduction Complements Pull-up network is complement of pull-down Parallel -> series, series -> parallel 1: Circuits & Layout
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Compound Gates Compound gates can do any inverting function Ex:
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Example: O3AI 1: Circuits & Layout
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Signal Strength Strength of signal
How close it approximates ideal voltage source VDD and GND rails are strongest 1 and 0 nMOS pass strong 0 But degraded or weak 1 pMOS pass strong 1 But degraded or weak 0 Thus nMOS are best for pull-down network 1: Circuits & Layout
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Pass Transistors Transistors can be used as switches
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Transmission Gates Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well 1: Circuits & Layout
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Tristates Tristate buffer produces Z when not enabled EN A Y Z 1
Z 1 1: Circuits & Layout
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Nonrestoring Tristate
Transmission gate acts as tristate buffer Only two transistors But nonrestoring Noise on A is passed on to Y 1: Circuits & Layout
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Tristate Inverter Tristate inverter produces restored output
Violates conduction complement rule Because we want a Z output 1: Circuits & Layout
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Multiplexers 2:1 multiplexer chooses between two inputs S D1 D0 Y X 1
X 1 1: Circuits & Layout
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Gate-Level Mux Design How many transistors are needed? 20
1: Circuits & Layout
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Transmission Gate Mux Nonrestoring mux uses two transmission gates
Only 4 transistors 1: Circuits & Layout
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Inverting Mux Inverting multiplexer Use compound AOI22
Or pair of tristate inverters Essentially the same thing Noninverting multiplexer adds an inverter 1: Circuits & Layout
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4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects
Two levels of 2:1 muxes Or four tristates 1: Circuits & Layout
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D Latch When CLK = 1, latch is transparent
D flows through to Q like a buffer When CLK = 0, the latch is opaque Q holds its old value independent of D a.k.a. transparent latch or level-sensitive latch 1: Circuits & Layout
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D Latch Design Multiplexer chooses D or old Q 1: Circuits & Layout
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D Latch Operation 1: Circuits & Layout
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D Flip-flop When CLK rises, D is copied to Q
At all other times, Q holds its value a.k.a. positive edge-triggered flip-flop, master-slave flip-flop 1: Circuits & Layout
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D Flip-flop Design Built from master and slave D latches
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D Flip-flop Operation 1: Circuits & Layout
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Race Condition Back-to-back flops can malfunction from clock skew
Second flip-flop fires late Sees first flip-flop change and captures its result Called hold-time failure or race condition 1: Circuits & Layout
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Nonoverlapping Clocks
Nonoverlapping clocks can prevent races As long as nonoverlap exceeds clock skew We will use them in this class for safe design Industry manages skew more carefully instead 1: Circuits & Layout
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Gate Layout Layout can be very time consuming
Design gates to fit together nicely Build a library of standard cells Standard cell design methodology VDD and GND should abut (standard height) Adjacent gates should satisfy design rules nMOS at bottom and pMOS at top All gates include well and substrate contacts 1: Circuits & Layout
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Example: Inverter 1: Circuits & Layout
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Example: NAND3 Horizontal N-diffusion and p-diffusion strips
Vertical polysilicon gates Metal1 VDD rail at top Metal1 GND rail at bottom 32 l by 40 l 1: Circuits & Layout
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Stick Diagrams Stick diagrams help plan layout quickly
Need not be to scale Draw with color pencils or dry-erase markers 1: Circuits & Layout
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Wiring Tracks A wiring track is the space required for a wire
4 l width, 4 l spacing from neighbor = 8 l pitch Transistors also consume one wiring track 1: Circuits & Layout
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Well spacing Wells must surround transistors by 6 l
Implies 12 l between opposite transistor flavors Leaves room for one wire track 1: Circuits & Layout
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Area Estimation Estimate area by counting wiring tracks
Multiply by 8 to express in l 1: Circuits & Layout
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Example: O3AI Sketch a stick diagram for O3AI and estimate area
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