1. Adopting New Learning Strategies for Computer Architecture in Higher Education Case Study: Building the S3 Microprocessor in 24 Hours Jean-Luc Dekeyser and A. Shadi Aljendi (jean-luc.dekeyser,ahmad.shadi.aljendi)@inria.fr 13/06/2015WCAE2015, 42nd ISCA, Portland, USA

2.  Second year computer science students  No digital systems or computer architecture prerequisites  No previous VHDL knowledge is required  Students have access to FPGA boards  The simulation tool is freeware  12 weeks  Theoretical lecture (1 hour)  Exercise session (1,5 hour)  Practical lab (2 hours x 12 = 24 hours) Learning ecosystem 13/06/2015WCAE2015, 42nd ISCA, Portland, USA

3. The course page 13/06/2015WCAE2015, 42nd ISCA, Portland, USA

4.  Harvard RISC processor  16-bit data bus  RTL  1 instruction per clock cycle  Easy to evolve microarchitecture Final product: the S3 processor 13/06/2015WCAE2015, 42nd ISCA, Portland, USA

5. Lesson 1: ISE for Nexys 13/06/2015WCAE2015, 42nd ISCA, Portland, USA

6.  Compilation  Loading  7-segment display  Your turn now 13/06/2015WCAE2015, 42nd ISCA, Portland, USA Lesson 1: ISE for Nexys

7. Lesson 2: Logic gates 13/06/2015WCAE2015, 42nd ISCA, Portland, USA

8. Lesson 3: 4-bit adder 13/06/2015WCAE2015, 42nd ISCA, Portland, USA

9. Lesson 3: 4-bit adder 13/06/2015WCAE2015, 42nd ISCA, Portland, USA

10. Lesson 4: 16-bit Display  1st sequential circuits  Counter  Clock devision 13/06/2015WCAE2015, 42nd ISCA, Portland, USA

11. Lesson 5: FSM 13/06/2015WCAE2015, 42nd ISCA, Portland, USA

12. Lesson 6: Registres 13/06/2015WCAE2015, 42nd ISCA, Portland, USA

13. Lesson 6: Registres 13/06/2015WCAE2015, 42nd ISCA, Portland, USA

14. Lesson 7: Fetch phase 13/06/2015WCAE2015, 42nd ISCA, Portland, USA

15. Lesson 8: The MOV instruction 13/06/2015WCAE2015, 42nd ISCA, Portland, USA

16. Lesson 8: The MOV instruction (An assembler in two minutes) 13/06/2015WCAE2015, 42nd ISCA, Portland, USA

17. Lesson 9: ALU onCode fonctioninstruction binaireCode Hexa SUBC00000001 0000 0000 00001000 ADD00010001 0001 0000 00001100 SUB00100001 0010 0000 00001200 ADDC00110001 0011 0000 00001300 INV01000001 0100 0000 00001400 AND01010001 0101 0000 00001500 OR01100001 0110 0000 00001600 INC01110001 0111 0000 00001700 CPL210000001 1000 0000 00001800 CONCAT10010001 1001 0000 00001900 ID10100001 1010 0000 00001A00 …. 13/06/2015WCAE2015, 42nd ISCA, Portland, USA

18. Lesson 10 : Immediate - condition  The MVI instruction  The instructions MZ and MNZ  The instructions MIZ and MINZ 13/06/2015WCAE2015, 42nd ISCA, Portland, USA

19. Lesson 11 : Assembler  Predicate calculation  The relative branch  The While construction 13/06/2015WCAE2015, 42nd ISCA, Portland, USA

20. Lessons 12 : The data memory  Harvard architecture  READ / WRITE instructions  program that inputs three 8- bit words from switches, store them in the memory at addresses 0, 1, 2 and then displays them one by one in the same order on the display.  An autonomous stack 13/06/2015WCAE2015, 42nd ISCA, Portland, USA

21. The S3 processor is complete 13/06/2015WCAE2015, 42nd ISCA, Portland, USA

22. Learning outcomes 13/06/2015WCAE2015, 42nd ISCA, Portland, USA

23. Website statistics 13/06/2015WCAE2015, 42nd ISCA, Portland, USA  Future directions  MOOC  HoMade