1. An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget Represented by: Majid Malaika Authors: Canturk Isci†, Alper Buyuktosunoglu†, Chen-Yong Cher†, Pradip Bose† and Margaret Martonosi

2. Computer Science and Engineering Agenda nBackground nMotivation nContribution nOverview of the global power management policy nCore Power Modes nGlobal Power Management Policies nIndependent Per-Core Power Management nSimulation nEvaluation nQ&A

3. Computer Science and Engineering Background nPower Management are desired for many reasons: n For portable devices n For Desktop systems n For Supercomputers P = V^2 * F nPower is proportional to voltage squared nCurrent is also proportional to voltage

4. Computer Science and Engineering Cont. Background nMulticore architecture has become more important than ever due to the Famous “Walls” nWith more cores on the dice, Power and temperature problems are becoming more and more crucial

5. Computer Science and Engineering Motivation nHow to enforce a power budget through global power manager? nHow to minimize power given a performance target?

6. Computer Science and Engineering Contributions nIntroduced the concept of Global Power Manager (PM) nDeveloped a fast static power management analysis tool nEvaluated different PM policies (with different focus such as prioritization, fairness, throughput)

7. Computer Science and Engineering Global CMP Power Management Overview nTo exploit the widely known variability in demand and characteristics of the input workloads nAdaptive response to “Phases” for power-efficient computing.

8. Computer Science and Engineering Cont. Global CMP Power Management Overview

9. Computer Science and Engineering Cont. Global CMP Power Management Overview the loop of PM’s work nPM periodically collects power-performance data from local monitors nPM reports it to OS nOS returns power budget, thread affinities, high-level scheduling and load-balancing plan to PM nPM decides the power-mode of each core based on those info

10. Computer Science and Engineering Cont. Global CMP Power Management Overview Preconditions Each core nhas its own dynamic controller nhas its power-performance monitor (e.g. current monitor, perf monitoring counter hw) ncan be running in multiple power modes

11. Computer Science and Engineering Core Power Modes nThree Power Modes: n Turbo n Efficient1(Eff1) n Efficient2(Eff2) nThe target is to achieve PowerSavings : PerformanceDegradation ratio of 3 : 1

12. Computer Science and Engineering Cont. Core Power Modes nTarget

13. Computer Science and Engineering Cont. Core Power Modes nTransition overhead between Power Modes n The duration of each monitored interval is called “Explore time” and is set to 500 MS. n Low overhead (1 to 4%)

14. Computer Science and Engineering Global Power Management Policies nIntroduced three policies for different objectives: n Priority n PullhiPushLo n MaxBIPS

15. Computer Science and Engineering Cont. Global Power Management Policies nPriority n Assigns Different Priority to different tasks n Highest Priority to highest Core (Example Core4) n Lowest Priority to Lowest Core (Example Core1) n In policy implementation it tries to run the highest AFAP n Prefer to slow down the first core in case of budget overshoot

16. Computer Science and Engineering Cont. Global Power Management Policies nPullhiPushLo n Tries to balance the power consumption of each core n It slows down the highest core in case of a budget overshoot n And by speeding up the lowest power core when there is available

17. Computer Science and Engineering Cont. Global Power Management Policies nMaxBIPS n Targets at optimizing the system throughput n Predicts and choose the Power Mode that Maximizes the throughput at each explore time n MaxBIPS does that by predicting the corresponding power and BIPS values for each power mode n It then chooses the combination with the highest throughput that satisfies the current power budget

18. Computer Science and Engineering Independent Per-Core Power Management nChip-Wide DVFS n Simpler alternative n No Synchronization across cores n Simplified OS and Hardware n All cores transition together into Turbo, Eff1, Eff2 at each explore time based on budget constraints

19. Computer Science and Engineering Simulation nBased on IBM Turandot simulator nPower statistics from IBM PowerTimer nThe list of core parameter

20. Computer Science and Engineering Cont. Simulation nTarget 3:1 nEstimation

21. Computer Science and Engineering Evaluation

22. Computer Science and Engineering Cont. Evaluation

23. Computer Science and Engineering Cont. Evaluation

24. Computer Science and Engineering Cont. Evaluation

25. Computer Science and Engineering References nC. Isci et al., "An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget"

26. Computer Science and Engineering Q&A The End