1. Test Data Generation for LRU Cache- Memory Testing Evgeny Kornikhin Moscow State University Institute for System Programming of RAS

2. testing by test programs add r1,r2,r3 sub r4, r1, r2 lw r5, r1, 0 lui r2, r1, r4 assembly program ( test program ) microprocessor Y/N

3. test program generation model of microprocessor coverage of test situations and dependencies (r-w, r-r) test templates test programs add r1,r2,r3 @ overflow lw r4, r3, c @ hit mov r2, 0xFF add r1,r2,r3 lw r4, r3, 0 (logical form) (executable form)

4. test program generation model of microprocessor coverage of test situations and dependencies (r-w, r-r) test templates test programs add r1,r2,r3 @ overflow lw r4, r3, c @ hit mov r2, 0xFF add r1,r2,r3 lw r4, r3, 0 (logical form) (executable form) R4000 add load args test situations rdrsrtoverflowregular... cache

5. test program generation model of microprocessor coverage of test situations and dependencies (r-w, r-r) test templates test programs add r1,r2,r3 @ overflow lw r4, r3, c @ hit mov r2, 0xFF add r1,r2,r3 lw r4, r3, 0 (logical form) (executable form) R4000 add load args test situations rdrsrtoverflowregular... cache add specific initialization of microprocessor (registers and cache)

6. cache-hit LOAD val, addr (val := memory[addr]) tag 0 ' value 0 ' set №0 set №s cache model tag 0 '' value 0 '' t'v't''v''

7. cache-hit LOAD val, addr (val := memory[addr]) st addr tag 0 ' value 0 ' tagset set №0 set №s t = t' or t = t'' cache model tag 0 '' value 0 '' t'v't''v'' t = t''

8. cache-miss LOAD val, addr (val := memory[addr]) st addr tag 0 ' value 0 ' tagset set №0 set №s t != t' and t != t'' cache model tag 0 '' value 0 '' t'v't''v'' next level evicted

9. problem again LOAD x, y @ hit STORE u, z @ miss LOAD z, y @ hit initial state of cache and registers = ?

10. key idea y  {a,b,c} u  {a,b,c} x = z add... load … sub … div … LOAD x, y @ hit ?? ?? ?? cache model test template constraint variable

11. fully associative cache N x x y y... z z {x,y,z,...} - current state

12. cache-hit hit(t) N x x y y... z z t t  x,y,z... 

13. cache-miss miss(t) N x x y y... z z t t  x,y,z...  new cache=  x,y,z...  t  \  ? 

14. cache-miss miss(t)→u N x x y y... z z t t  x,y,z...  new cache=  x,y,z...  t  \  u  u  x,y,z... 

15. lru(u) hit x1 hit x2 miss x3->x4 hit x5 miss t->u u = x2 {x3, x5} = L\{u} counter(u)=min L

16. lru(u) hit x1 hit x2 miss x3->x4 hit x5 miss t->u u = x1 {x2, x3, x5} = L\{u} there are another cases L

17. example LOAD x, y @ hit STORE u, z @ miss LOAD z, y @ hit N = 3 y     z  →z0 z0  y  z  \  z0  z0=   \  z0  y  initial state:

18. example y  z  z0  y  z  \  z0  z0=   \  z0  y  y  z  y    z 

19. common cache z x R(x) R(y) R(z) x y z y

20. common cache hit(t) miss(t)→u t  L u  L t  L new cache=L  {t}\{u} R(t) = R(u) lru(u)

21. lru(u) hit x1 hit x2 miss x3→x4 hit x5 miss t→u u = x2 {x3, x5}∩R(u) = (L\{u})∩R(u)

22. example x1,x2  {a1,a2,b1,b2,c1,c2} x3  {a1,a2,b1,b2,c1,c2} R(x3) = R(y3) x4  {a1,...,c2,x3}\{y3} x5  {a1,...,c2,x3}\{y3} {y3} = ({a1,...,c2}\{x1,x2, y3})∩R(y3) {y5} = ({a1...c2,x3}\{y3,y5, x3,x4})∩R(y5) y5 = x2 y3 = c2

23. solver SAT modulo theories (bit-vectors) Yices x  {a,b,c} y  {a,b,c} x = z (assert (or (= x a) (= x b)(= x c))) (assert (and (/= y a) (/= y b)(/= y c))) (check) SMT

24. contacts http://tesla-project.googlecode.com http://hardware.ispras.ru kornevgen@gmail.com